!!!!    6    0    1  986583776  Va477                                         

! Device           : 2149
! Function         : Static RAM 3-state 1k x 4
! revision         : B.01.00
! safeguard        : high_out_mos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

vector cycle   400n   ! If the outputs are pulled down, use vc = 700n,
receive delay  300n   ! rd = 600n

!  This test includes an option for testing Chip Select, pin 8.
!  This device has tri-state outputs, therefore the outputs must be
!  either pulled up or down to test the chip disabled condition.
!  Please refer to the last subroutine for further details.

assign    VCC            to pins   18
assign    GND            to pins    9

assign    Address        to pins   15,16,17,1,2,3,4,7,6,5

assign    Data           to pins   11,12,13,14
assign    Data_D0        to pins   14   !AT Added for minimum pin test.
assign    Data_D1        to pins   13   !AT Added for minimum pin test.
assign    Data_D2        to pins   12   !AT Added for minimum pin test.
assign    Data_D3        to pins   11   !AT Added for minimum pin test.

assign    CSbar                 to pins    8
assign    WEbar                 to pins   10

family    TTL

power     VCC, GND

inputs    Address, WEbar, CSbar

bidirectional  Data
bidirectional  Data_D0, Data_D1, Data_D2, Data_D3 !AT Added for min. pin test.

set load on groups Data      to pull up

when     CSbar    is    "1"   inactive    Data
when     WEbar    is    "0"   inputs      Data
when     WEbar    is    "1"   outputs     Data

trace    Data  to  Address, WEbar, CSbar

disable   Data   with  CSbar     to   "1"

!***************************************************************
!***************************************************************

vector    Reset
     set  WEbar      to   "1"
     set  CSbar      to   "1"
end vector

vector    CSbar_true
     set  WEbar      to   "k"
     set  CSbar      to   "0"
end vector

vector    CSbar_false
     set  Address    to   "kkkkkkkkkk"
     set  WEbar      to   "k"
     set  CSbar      to   "1"
end vector

vector    Write_enable
     set  Address    to   "kkkkkkkkkk"
     set  WEbar      to   "0"
     set  CSbar      to   "k"
end vector

vector    Read_enable
     set  Address    to   "kkkkkkkkkk"
     set  WEbar      to   "1"
     set  CSbar      to   "k"
end vector

vector    Address_0000000000
     initialize to  CSbar_true
     set  Address   to   "0000000000"
end vector

vector    Address_0000000001
     initialize to  CSbar_true
     set  Address   to   "0000000001"
end vector

vector    Address_0000000011
     initialize to  CSbar_true
     set  Address   to   "0000000011"
end vector

vector    Address_0000000111
     initialize to  CSbar_true
     set  Address   to   "0000000111"
end vector

vector    Address_0000001111
     initialize to  CSbar_true
     set  Address   to   "0000001111"
end vector

vector    Address_0000011111
     initialize to  CSbar_true
     set  Address   to   "0000011111"
end vector

vector    Address_0000111111
     initialize to  CSbar_true
     set  Address   to   "0000111111"
end vector

vector    Address_0001111111
     initialize to  CSbar_true
     set  Address   to   "0001111111"
end vector

vector    Address_0011111111
     initialize to  CSbar_true
     set  Address   to   "0011111111"
end vector

vector    Address_0111111111
     initialize to  CSbar_true
     set  Address   to   "0111111111"
end vector

vector    Address_1111111111
     initialize to  CSbar_true
     set  Address   to   "1111111111"
end vector

vector    Data_write_0000
     initialize to  Write_enable
     drive  Data
     set Data       to   "0000"
end vector

vector    Data_write_0001
     initialize to  Write_enable
     drive  Data
     set Data       to   "0001"
end vector

vector    Data_write_0011
     initialize to  Write_enable
     drive  Data
     set Data       to   "0011"
end vector

vector    Data_write_0111
     initialize to  Write_enable
     drive  Data
     set Data       to   "0111"
end vector

vector    Data_write_1111
     initialize to  Write_enable
     drive  Data
     set Data       to   "1111"
end vector

vector    Data_write_0101
     initialize to  Write_enable
     drive  Data
     set Data       to   "0101"
end vector

vector    Data_write_1010
     initialize to  Write_enable
     drive  Data
     set Data       to   "1010"
end vector

vector    Data_read_0000
     initialize to  Read_enable
     receive  Data
     set Data       to   "0000"
end vector

vector    Data_read_0001
     initialize to  Read_enable
     receive  Data
     set Data       to   "0001"
end vector

vector    Data_read_0011
     initialize to  Read_enable
     receive  Data
     set Data       to   "0011"
end vector

vector    Data_read_0111
     initialize to  Read_enable
     receive  Data
     set Data       to   "0111"
end vector

vector    Data_read_1111
     initialize to  Read_enable
     receive  Data
     set Data       to   "1111"
end vector

vector    Data_read_0101
     initialize to  Read_enable
     receive  Data
     set Data       to   "0101"
end vector

vector    Data_read_1010
     initialize to  Read_enable
     receive  Data
     set Data       to   "1010"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector    Data_write_D0_0
     initialize to  Write_enable
     drive  Data_D0
     set Data_D0    to   "0"
end vector

vector    Data_write_D0_1
     initialize to  Write_enable
     drive  Data_D0
     set Data_D0    to   "1"
end vector

vector    Data_write_D1_0
     initialize to  Write_enable
     drive  Data_D1
     set Data_D1    to   "0"
end vector

vector    Data_write_D1_1
     initialize to  Write_enable
     drive  Data_D1
     set Data_D1    to   "1"
end vector

vector    Data_write_D2_0
     initialize to  Write_enable
     drive  Data_D2
     set Data_D2    to   "0"
end vector

vector    Data_write_D2_1
     initialize to  Write_enable
     drive  Data_D2
     set Data_D2    to   "1"
end vector

vector    Data_write_D3_0
     initialize to  Write_enable
     drive  Data_D3
     set Data_D3    to   "0"
end vector

vector    Data_write_D3_1
     initialize to  Write_enable
     drive  Data_D3
     set Data_D3    to   "1"
end vector

vector    Data_read_D0_0
     initialize to  Read_enable
     receive  Data_D0
     set Data_D0    to   "0"
end vector

vector    Data_read_D0_1
     initialize to  Read_enable
     receive  Data_D0
     set Data_D0    to   "1"
end vector

vector    Data_read_D1_0
     initialize to  Read_enable
     receive  Data_D1
     set Data_D1    to   "0"
end vector

vector    Data_read_D1_1
     initialize to  Read_enable
     receive  Data_D1
     set Data_D1    to   "1"
end vector

vector    Data_read_D2_0
     initialize to  Read_enable
     receive  Data_D2
     set Data_D2    to   "0"
end vector

vector    Data_read_D2_1
     initialize to  Read_enable
     receive  Data_D2
     set Data_D2    to   "1"
end vector

vector    Data_read_D3_0
     initialize to  Read_enable
     receive  Data_D3
     set Data_D3    to   "0"
end vector

vector    Data_read_D3_1
     initialize to  Read_enable
     receive  Data_D3
     set Data_D3    to   "1"
end vector

!***************************************************************
!***************************************************************

sub  Write_data (Address, Data)
     execute   Address
     execute   Data
     execute   Reset
end sub

sub  Read_data (Address, Data)
     execute   Address
     execute   Data
end sub

sub  Test_CSbar
     execute   Reset
     execute   Address_0000000000
     execute   Data_write_0101
     execute   Reset
     execute   CSbar_false
     execute   Data_read_1111    ! Use this line if outputs tied high
end  sub

!***************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit   "awaretest D0 Test"

     execute   Reset

     call Write_data (Address_0000000000, Data_write_D0_0)
     call Read_data (Address_0000000000, Data_read_D0_0)

     call Write_data (Address_0000000000, Data_write_D0_1)
     call Read_data (Address_0000000000, Data_read_D0_1)

end unit

unit   "awaretest D1 Test"

     execute   Reset

     call Write_data (Address_0000000000, Data_write_D1_0)
     call Read_data (Address_0000000000, Data_read_D1_0)

     call Write_data (Address_0000000000, Data_write_D1_1)
     call Read_data (Address_0000000000, Data_read_D1_1)

end unit

unit   "awaretest D2 Test"

     execute   Reset

     call Write_data (Address_0000000000, Data_write_D2_0)
     call Read_data (Address_0000000000, Data_read_D2_0)

     call Write_data (Address_0000000000, Data_write_D2_1)
     call Read_data (Address_0000000000, Data_read_D2_1)

end unit

unit   "awaretest D3 Test"

     execute   Reset

     call Write_data (Address_0000000000, Data_write_D3_0)
     call Read_data (Address_0000000000, Data_read_D3_0)

     call Write_data (Address_0000000000, Data_write_D3_1)
     call Read_data (Address_0000000000, Data_read_D3_1)

end unit

unit "Test Address/Data lines "

     execute   Reset

     call Write_data (Address_0000000000, Data_write_0000)
     call Write_data (Address_0000000001, Data_write_0001)
     call Write_data (Address_0000000011, Data_write_0011)
     call Write_data (Address_0000000111, Data_write_0111)
     call Write_data (Address_0000001111, Data_write_1111)
     call Write_data (Address_0000011111, Data_write_0001)
     call Write_data (Address_0000111111, Data_write_0011)
     call Write_data (Address_0001111111, Data_write_0111)
     call Write_data (Address_0011111111, Data_write_1111)
     call Write_data (Address_0111111111, Data_write_0101)
     call Write_data (Address_1111111111, Data_write_1010)

     call Read_data (Address_0000000000, Data_read_0000)
     call Read_data (Address_0000000001, Data_read_0001)
     call Read_data (Address_0000000011, Data_read_0011)
     call Read_data (Address_0000000111, Data_read_0111)
     call Read_data (Address_0000001111, Data_read_1111)
     call Read_data (Address_0000011111, Data_read_0001)
     call Read_data (Address_0000111111, Data_read_0011)
     call Read_data (Address_0001111111, Data_read_0111)
     call Read_data (Address_0011111111, Data_read_1111)
     call Read_data (Address_0111111111, Data_read_0101)
     call Read_data (Address_1111111111, Data_read_1010)
end unit

unit  "Test chip select "
     call Test_CSbar
end unit

!    End of test