!!!!    6    0    1  986417779  Vdc90                                         

! Device           : 2101
! Function         : Static RAM 3-state 256 x 4
! revision         : B.01.00
! safeguard        : med_out_mos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

vector cycle 1500n
receive delay 1400n

assign    VCC            to pins   22
assign    GND            to pins   8

assign    Address        to pins   7,6,5,21,1,2,3,4

assign    Data_in        to pins   15,13,11,9
assign    Data_out       to pins   16,14,12,10

assign  Data_in_D0  to pins 9    !AT Added for minimum pin test.
assign  Data_in_D1  to pins 11   !AT Added for minimum pin test.
assign  Data_in_D2  to pins 13   !AT Added for minimum pin test.
assign  Data_in_D3  to pins 15   !AT Added for minimum pin test.

assign  Data_out_D0 to pins 10   !AT Added for minimum pin test.
assign  Data_out_D1 to pins 12   !AT Added for minimum pin test.
assign  Data_out_D2 to pins 14   !AT Added for minimum pin test.
assign  Data_out_D3 to pins 16   !AT Added for minimum pin test.

assign    Chip_enable_1_bar     to pins   19
assign    Chip_enable_2         to pins   17
assign    Chip_enables          to pins   19,17
assign    Output_disable        to pins   18

assign    Write_enable_bar      to pins   20

family    TTL

power     VCC, GND

inputs    Address, Data_in, Write_enable_bar, Output_disable
inputs    Chip_enable_1_bar, Chip_enable_2, Chip_enables
inputs    Data_in_D0, Data_in_D1, Data_in_D2, Data_in_D3      !AT Added for min pin test.

outputs   Data_out
outputs   Data_out_D0, Data_out_D1, Data_out_D2, Data_out_D3  !AT Added for min pin test.

set load on groups Data_out      to pull up

when     Chip_enable_1_bar    is "1"   inactive Data_out
when     Chip_enable_2        is "0"   inactive Data_out
when     Output_disable       is "1"   inactive Data_out

trace    Data_out  to  Address, Data_in, Write_enable_bar, Output_disable
trace    Data_out  to  Chip_enable_1_bar, Chip_enable_2, Chip_enables

disable   Data_out  with Chip_enable_1_bar     to   "1"
disable   Data_out  with Chip_enable_2         to   "0"
disable   Data_out  with Output_disable        to   "1"

!***************************************************************
!***************************************************************

vector    Disable
set  Write_enable_bar    to   "1"
set  Chip_enables        to   "10"
set  Output_disable      to   "1"
end vector

vector    Disable_output
set  Address             to   "kkkkkkkk"
set  Write_enable_bar    to   "k"
set  Chip_enables        to   "01"
set  Output_disable      to   "1"
end vector

vector    Write_enable_true
set  Address             to   "kkkkkkkk"
set  Data_in             to   "kkkk"
set  Write_enable_bar    to   "0"
set  Chip_enables        to   "kk"
set  Output_disable      to   "k"
end vector

vector    Write_enable_false
set  Address             to   "kkkkkkkk"
set  Data_in             to   "kkkk"
set  Write_enable_bar    to   "1"
set  Chip_enables        to   "10"
set  Output_disable      to   "k"
end vector

vector    Chip_enable
set  Address             to   "kkkkkkkk"
set  Write_enable_bar    to   "k"
set  Chip_enables        to   "01"
set  Output_disable      to   "0"
end vector

vector    Chip_enable_1_false
set  Address             to   "kkkkkkkk"
set  Write_enable_bar    to   "k"
set  Chip_enables        to   "11"
set  Output_disable      to   "k"
end vector

vector    Chip_enable_2_false
set  Address             to   "kkkkkkkk"
set  Write_enable_bar    to   "k"
set  Chip_enables        to   "00"
set  Output_disable      to   "k"
end vector

vector    Address_00000000
initialize to  Disable
set  Address   to   "00000000"
end vector

vector    Address_00000001
initialize to  Disable
set  Address   to   "00000001"
end vector

vector    Address_00000011
initialize to  Disable
set  Address   to   "00000011"
end vector

vector    Address_00000111
initialize to  Disable
set  Address   to   "00000111"
end vector

vector    Address_00001111
initialize to  Disable
set  Address   to   "00001111"
end vector

vector    Address_00011111
initialize to  Disable
set  Address   to   "00011111"
end vector

vector    Address_00111111
initialize to  Disable
set  Address   to   "00111111"
end vector

vector    Address_01111111
initialize to  Disable
set  Address   to   "01111111"
end vector
vector    Address_11111111
initialize to  Disable
set  Address   to   "11111111"
end vector

vector    Data_write_0000
initialize to  Chip_enable
set Data_in    to   "0000"
end vector

vector    Data_write_0001
initialize to  Chip_enable
set Data_in    to   "0001"
end vector

vector    Data_write_0011
initialize to  Chip_enable
set Data_in    to   "0011"
end vector

vector    Data_write_0111
initialize to  Chip_enable
set Data_in    to   "0111"
end vector

vector    Data_write_1111
initialize to  Chip_enable
set Data_in    to   "1111"
end vector

vector    Data_write_1110
initialize to  Chip_enable
set Data_in    to   "1110"
end vector

vector    Data_write_1100
initialize to  Chip_enable
set Data_in    to   "1100"
end vector

vector    Data_write_1000
initialize to  Chip_enable
set Data_in    to   "1000"
end vector

vector    Data_write_1010
initialize to  Chip_enable
set Data_in    to   "1010"
end vector

vector    Data_write_1111_disabled
set Address           to  "kkkkkkkk"
set Write_enable_bar  to  "k"
set Chip_enables      to  "kk"
set Output_disable    to  "k"
set Data_in           to  "1111"
end vector


vector    Data_read_0000
initialize to  Chip_enable
set Data_out   to   "0000"
end vector

vector    Data_read_0001
initialize to  Chip_enable
set Data_out   to   "0001"
end vector

vector    Data_read_0011
initialize to  Chip_enable
set Data_out   to   "0011"
end vector

vector    Data_read_0111
initialize to  Chip_enable
set Data_out   to   "0111"
end vector

vector    Data_read_1111
initialize to  Chip_enable
set Data_out   to   "1111"
end vector

vector    Data_read_1110
initialize to  Chip_enable
set Data_out   to   "1110"
end vector

vector    Data_read_1100
initialize to  Chip_enable
set Data_out   to   "1100"
end vector

vector    Data_read_1000
initialize to  Chip_enable
set Data_out   to   "1000"
end vector

vector    Data_read_1010
initialize to  Chip_enable
set Data_out   to   "1010"
end vector


vector    Address_00000000_Disable_output
initialize to  Disable_output
set  Address   to   "00000000"
end vector

vector    Data_read_1111_Disable_output
initialize to  Disable_output
set Data_out   to   "1111"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector    Data_write_D0_0
   initialize to  Chip_enable
   set Data_in_D0           to   "0"
end vector

vector    Data_write_D0_1
   initialize to  Chip_enable
   set Data_in_D0           to   "1"
end vector

vector    Data_write_D1_0
   initialize to  Chip_enable
   set Data_in_D1           to   "0"
end vector

vector    Data_write_D1_1
   initialize to  Chip_enable
   set Data_in_D1           to   "1"
end vector

vector    Data_write_D2_0
   initialize to  Chip_enable
   set Data_in_D2           to   "0"
end vector

vector    Data_write_D2_1
   initialize to  Chip_enable
   set Data_in_D2           to   "1"
end vector

vector    Data_write_D3_0
   initialize to  Chip_enable
   set Data_in_D3           to   "0"
end vector

vector    Data_write_D3_1
   initialize to  Chip_enable
   set Data_in_D3           to   "1"
end vector

vector    Data_read_D0_0
   initialize to  Chip_enable
   set Data_out_D0          to   "0"
end vector

vector    Data_read_D0_1
   initialize to  Chip_enable
   set Data_out_D0          to   "1"
end vector

vector    Data_read_D1_0
   initialize to  Chip_enable
   set Data_out_D1          to   "0"
end vector

vector    Data_read_D1_1
   initialize to  Chip_enable
   set Data_out_D1          to   "1"
end vector

vector    Data_read_D2_0
   initialize to  Chip_enable
   set Data_out_D2          to   "0"
end vector

vector    Data_read_D2_1
   initialize to  Chip_enable
   set Data_out_D2          to   "1"
end vector

vector    Data_read_D3_0
   initialize to  Chip_enable
   set Data_out_D3          to   "0"
end vector

vector    Data_read_D3_1
   initialize to  Chip_enable
   set Data_out_D3          to   "1"
end vector

vector    WEb_lo_D0
   set  Address             to   "kkkkkkkk"
   set  Data_in_D0          to   "k"
   set  Write_enable_bar    to   "0"
   set  Chip_enables        to   "kk"
   set  Output_disable      to   "k"
end vector

vector    WEb_hi_D0
   set  Address             to   "kkkkkkkk"
   set  Data_in_D0          to   "k"
   set  Write_enable_bar    to   "1"
   set  Chip_enables        to   "10"
   set  Output_disable      to   "k"
end vector

vector    WEb_lo_D1
   set  Address             to   "kkkkkkkk"
   set  Data_in_D1          to   "k"
   set  Write_enable_bar    to   "0"
   set  Chip_enables        to   "kk"
   set  Output_disable      to   "k"
end vector

vector    WEb_hi_D1
   set  Address             to   "kkkkkkkk"
   set  Data_in_D1          to   "k"
   set  Write_enable_bar    to   "1"
   set  Chip_enables        to   "10"
   set  Output_disable      to   "k"
end vector

vector    WEb_lo_D2
   set  Address             to   "kkkkkkkk"
   set  Data_in_D2          to   "k"
   set  Write_enable_bar    to   "0"
   set  Chip_enables        to   "kk"
   set  Output_disable      to   "k"
end vector

vector    WEb_hi_D2
   set  Address             to   "kkkkkkkk"
   set  Data_in_D2          to   "k"
   set  Write_enable_bar    to   "1"
   set  Chip_enables        to   "10"
   set  Output_disable      to   "k"
end vector

vector    WEb_lo_D3
   set  Address             to   "kkkkkkkk"
   set  Data_in_D3          to   "k"
   set  Write_enable_bar    to   "0"
   set  Chip_enables        to   "kk"
   set  Output_disable      to   "k"
end vector

vector    WEb_hi_D3
   set  Address             to   "kkkkkkkk"
   set  Data_in_D3          to   "k"
   set  Write_enable_bar    to   "1"
   set  Chip_enables        to   "10"
   set  Output_disable      to   "k"
end vector

!***************************************************************
!***************************************************************

sub  Write_data (Address, Data)
execute   Address
execute   Data
execute   Write_enable_true
execute   Write_enable_false
end sub

sub  Read_data (Address, Data)
execute   Address
execute   Data
end sub

!AT The following subroutines have been added for a minimum pins test.
!AT Vectors in the subroutine "Write_data" reference the entire data bus.
!AT Therefore this subroutine was copied and modified to reference only
!AT a single pin of the data bus. The subroutine "Read_data" did not
!AT require any modification as all references to the data bus are made
!AT via a passed parameter (Data). This reference can be modified in the
!AT call statement.

sub  Write_data_Dx (Address, Data_Dx, WEb_lo_Dx, WEb_hi_Dx)
     execute   Address
     execute   Data_Dx
     execute   WEb_lo_Dx
     execute   WEb_hi_Dx
end sub

!***************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit   "awaretest D0 Test"

    call Write_data_Dx (Address_00000000, Data_write_D0_0, WEb_lo_D0, WEb_hi_D0)
    call Read_data (Address_00000000, Data_read_D0_0)

    call Write_data_Dx (Address_00000000, Data_write_D0_1, WEb_lo_D0, WEb_hi_D0)
    call Read_data (Address_00000000, Data_read_D0_1)

end unit

unit   "awaretest D1 Test"

    call Write_data_Dx (Address_00000000, Data_write_D1_0, WEb_lo_D1, WEb_hi_D1)
    call Read_data (Address_00000000, Data_read_D1_0)

    call Write_data_Dx (Address_00000000, Data_write_D1_1, WEb_lo_D1, WEb_hi_D1)
    call Read_data (Address_00000000, Data_read_D1_1)

end unit

unit   "awaretest D2 Test"

    call Write_data_Dx (Address_00000000, Data_write_D2_0, WEb_lo_D2, WEb_hi_D2)
    call Read_data (Address_00000000, Data_read_D2_0)

    call Write_data_Dx (Address_00000000, Data_write_D2_1, WEb_lo_D2, WEb_hi_D2)
    call Read_data (Address_00000000, Data_read_D2_1)

end unit

unit   "awaretest D3 Test"

    call Write_data_Dx (Address_00000000, Data_write_D3_0, WEb_lo_D3, WEb_hi_D3)
    call Read_data (Address_00000000, Data_read_D3_0)

    call Write_data_Dx (Address_00000000, Data_write_D3_1, WEb_lo_D3, WEb_hi_D3)
    call Read_data (Address_00000000, Data_read_D3_1)

end unit

unit "RAM test"
call Write_data (Address_00000000, Data_write_0000)
call Write_data (Address_00000001, Data_write_0001)
call Write_data (Address_00000011, Data_write_0011)
call Write_data (Address_00000111, Data_write_0111)
call Write_data (Address_00001111, Data_write_1111)
call Write_data (Address_00011111, Data_write_1110)
call Write_data (Address_00111111, Data_write_1100)
call Write_data (Address_01111111, Data_write_1000)
call Write_data (Address_11111111, Data_write_1010)
call Read_data (Address_00000000, Data_read_0000)
call Read_data (Address_00000001, Data_read_0001)
call Read_data (Address_00000011, Data_read_0011)
call Read_data (Address_00000111, Data_read_0111)
call Read_data (Address_00001111, Data_read_1111)
call Read_data (Address_00011111, Data_read_1110)
call Read_data (Address_00111111, Data_read_1100)
call Read_data (Address_01111111, Data_read_1000)
call Read_data (Address_11111111, Data_read_1010)
end unit

unit "Test Chip_enable_1_false"
call Write_data (Address_00000000, Data_write_0000)
execute Address_00000000
execute Chip_enable_1_false
execute Data_write_1111_disabled
execute Write_enable_true
execute Write_enable_false
call Read_data (Address_00000000, Data_read_0000)
end unit

unit "Test Chip_enable_2_false"
call Write_data (Address_00000000, Data_write_0000)
execute Address_00000000
execute Chip_enable_2_false
execute Data_write_1111_disabled
execute Write_enable_true
execute Write_enable_false
call Read_data (Address_00000000, Data_read_0000)
end unit

!    If PULL-UPS exist on the outputs the following unit can be included
!    to verify that the Output_disable pin is not stuck-at-0.

!unit "Test Output_disable"
!call Write_data (Address_00000000, Data_write_0000)
!execute Address_00000000_Disable_output
!execute Data_Read_1111_Disable_output
!end unit


!    End of test