!!!! 6 0 1 986773908 Vdb27 ! Device : 2018d ! Function : Static RAM 3-state 2k x 8 ! revision : B.01.00 ! safeguard : high_out_mos ! Modifications : Modified for AwareTest xi ! warning "This library has not been verified with hardware." sequential vector cycle 400n ! If the outputs are pulled down, use vc = 500n, receive delay 300n ! rd = 400n assign VCC to pins 24 assign GND to pins 12 assign Address to pins 19,22,23,1,2,3,4,5,6,7 assign Address to pins 8 assign Data to pins 17,16,15,14,13,11,10,9 assign Data_D0 to pins 9 !AT Added for minimum pin test. assign Data_D1 to pins 10 !AT Added for minimum pin test. assign Data_D2 to pins 11 !AT Added for minimum pin test. assign Data_D3 to pins 13 !AT Added for minimum pin test. assign Data_D4 to pins 14 !AT Added for minimum pin test. assign Data_D5 to pins 15 !AT Added for minimum pin test. assign Data_D6 to pins 16 !AT Added for minimum pin test. assign Data_D7 to pins 17 !AT Added for minimum pin test. assign CSbar to pins 18 assign WEbar to pins 21 assign OEbar to pins 20 format hexadecimal Address, Data family TTL power VCC, GND inputs Address, WEbar, CSbar,OEbar bidirectional Data bidirectional Data_D0, Data_D1, Data_D2, Data_D3 !AT Added for min. pin test. bidirectional Data_D4, Data_D5, Data_D6, Data_D7 !AT Added for min. pin test. disable Data with OEbar to "1" disable Data with CSbar to "1" when OEbar is "1" inactive Data when CSbar is "1" inactive Data when WEbar is "0" inputs Data when WEbar is "1" outputs Data trace Data to Address, WEbar, CSbar, OEbar, Data !*************************************************************** !*************************************************************** vector Reset set WEbar to "1" ! set CSbar to "1" set CSbar to "0" ! 11,12,13 has CSbar tied to gnd rje set OEbar to "0" end vector vector CSbar_true set Address to "kkk" set WEbar to "k" set CSbar to "0" set OEbar to "k" end vector vector OEbar_false set Address to "kkk" set WEbar to "k" set CSbar to "0" set OEbar to "1" end vector vector Write_enable set Address to "kkk" set WEbar to "0" set CSbar to "k" set OEbar to "k" end vector vector Read_enable set Address to "kkk" set WEbar to "1" set CSbar to "k" set OEbar to "k" end vector vector Address_Counter initialize to CSbar_true set Address to "7FF" upcounter Address end vector vector Address_Counter_1 initialize to CSbar_true set Address to "000" downcounter Address end vector vector Data_write_AA initialize to Write_enable drive Data set Data to "AA" end vector vector Data_write_55 initialize to Write_enable drive Data set Data to "55" end vector vector Data_read initialize to Read_enable receive Data set Data to "00" end vector !AT The following vectors have been added for a minimum pins test. Any !AT vectors that references the data bus was copied and modified to reference !AT only a single pin of the data bus. vector Address_000 initialize to CSbar_true set Address to "000" end vector vector Data_write_D0_0 initialize to Write_enable drive Data_D0 set Data_D0 to "0" end vector vector Data_write_D0_1 initialize to Write_enable drive Data_D0 set Data_D0 to "1" end vector vector Data_write_D1_0 initialize to Write_enable drive Data_D1 set Data_D1 to "0" end vector vector Data_write_D1_1 initialize to Write_enable drive Data_D1 set Data_D1 to "1" end vector vector Data_write_D2_0 initialize to Write_enable drive Data_D2 set Data_D2 to "0" end vector vector Data_write_D2_1 initialize to Write_enable drive Data_D2 set Data_D2 to "1" end vector vector Data_write_D3_0 initialize to Write_enable drive Data_D3 set Data_D3 to "0" end vector vector Data_write_D3_1 initialize to Write_enable drive Data_D3 set Data_D3 to "1" end vector vector Data_write_D4_0 initialize to Write_enable drive Data_D4 set Data_D4 to "0" end vector vector Data_write_D4_1 initialize to Write_enable drive Data_D4 set Data_D4 to "1" end vector vector Data_write_D5_0 initialize to Write_enable drive Data_D5 set Data_D5 to "0" end vector vector Data_write_D5_1 initialize to Write_enable drive Data_D5 set Data_D5 to "1" end vector vector Data_write_D6_0 initialize to Write_enable drive Data_D6 set Data_D6 to "0" end vector vector Data_write_D6_1 initialize to Write_enable drive Data_D6 set Data_D6 to "1" end vector vector Data_write_D7_0 initialize to Write_enable drive Data_D7 set Data_D7 to "0" end vector vector Data_write_D7_1 initialize to Write_enable drive Data_D7 set Data_D7 to "1" end vector vector Data_read_D0_0 initialize to Read_enable receive Data_D0 set Data_D0 to "0" end vector vector Data_read_D0_1 initialize to Read_enable receive Data_D0 set Data_D0 to "1" end vector vector Data_read_D1_0 initialize to Read_enable receive Data_D1 set Data_D1 to "0" end vector vector Data_read_D1_1 initialize to Read_enable receive Data_D1 set Data_D1 to "1" end vector vector Data_read_D2_0 initialize to Read_enable receive Data_D2 set Data_D2 to "0" end vector vector Data_read_D2_1 initialize to Read_enable receive Data_D2 set Data_D2 to "1" end vector vector Data_read_D3_0 initialize to Read_enable receive Data_D3 set Data_D3 to "0" end vector vector Data_read_D3_1 initialize to Read_enable receive Data_D3 set Data_D3 to "1" end vector vector Data_read_D4_0 initialize to Read_enable receive Data_D4 set Data_D4 to "0" end vector vector Data_read_D4_1 initialize to Read_enable receive Data_D4 set Data_D4 to "1" end vector vector Data_read_D5_0 initialize to Read_enable receive Data_D5 set Data_D5 to "0" end vector vector Data_read_D5_1 initialize to Read_enable receive Data_D5 set Data_D5 to "1" end vector vector Data_read_D6_0 initialize to Read_enable receive Data_D6 set Data_D6 to "0" end vector vector Data_read_D6_1 initialize to Read_enable receive Data_D6 set Data_D6 to "1" end vector vector Data_read_D7_0 initialize to Read_enable receive Data_D7 set Data_D7 to "0" end vector vector Data_read_D7_1 initialize to Read_enable receive Data_D7 set Data_D7 to "1" end vector !*************************************************************** !*************************************************************** !AT The following AwareTest units have been added for minimum pins tests. Each !AT unit tests a separate data pin starting with D0. unit "awaretest D0 Test" execute Reset execute Address_000 execute Data_write_D0_0 execute Reset execute Address_000 execute Data_read_D0_0 execute Reset execute Address_000 execute Data_write_D0_1 execute Reset execute Address_000 execute Data_read_D0_1 end unit unit "awaretest D1 Test" execute Reset execute Address_000 execute Data_write_D1_0 execute Reset execute Address_000 execute Data_read_D1_0 execute Reset execute Address_000 execute Data_write_D1_1 execute Reset execute Address_000 execute Data_read_D1_1 end unit unit "awaretest D2 Test" execute Reset execute Address_000 execute Data_write_D2_0 execute Reset execute Address_000 execute Data_read_D2_0 execute Reset execute Address_000 execute Data_write_D2_1 execute Reset execute Address_000 execute Data_read_D2_1 end unit unit "awaretest D3 Test" execute Reset execute Address_000 execute Data_write_D3_0 execute Reset execute Address_000 execute Data_read_D3_0 execute Reset execute Address_000 execute Data_write_D3_1 execute Reset execute Address_000 execute Data_read_D3_1 end unit unit "awaretest D4 Test" execute Reset execute Address_000 execute Data_write_D4_0 execute Reset execute Address_000 execute Data_read_D4_0 execute Reset execute Address_000 execute Data_write_D4_1 execute Reset execute Address_000 execute Data_read_D4_1 end unit unit "awaretest D5 Test" execute Reset execute Address_000 execute Data_write_D5_0 execute Reset execute Address_000 execute Data_read_D5_0 execute Reset execute Address_000 execute Data_write_D5_1 execute Reset execute Address_000 execute Data_read_D5_1 end unit unit "awaretest D6 Test" execute Reset execute Address_000 execute Data_write_D6_0 execute Reset execute Address_000 execute Data_read_D6_0 execute Reset execute Address_000 execute Data_write_D6_1 execute Reset execute Address_000 execute Data_read_D6_1 end unit unit "awaretest D7 Test" execute Reset execute Address_000 execute Data_write_D7_0 execute Reset execute Address_000 execute Data_read_D7_0 execute Reset execute Address_000 execute Data_write_D7_1 execute Reset execute Address_000 execute Data_read_D7_1 end unit ! This test was modified from the standard library test to write an ! alternating bit pattern to ALL addresses in RAM. - bs unit "Write AA/55 pattern" execute Reset preset counter Address_Counter ! address to $7FF repeat 1024 times ! starting at $000 to $7FF write count Address_Counter ! AA to even addresses and 55 to execute Data_write_AA ! odd addresses. execute Reset count Address_Counter execute Data_write_55 execute Reset end repeat preset counter Address_Counter_1 ! address to $000 repeat 1024 times ! starting at $7FF to $000 read count Address_Counter_1 compress ! then write. AA to odd addresses, execute Data_read compress ! 55 to even address. execute Data_write_AA compress execute Reset compress count Address_Counter_1 compress execute Data_read compress execute Data_write_55 compress execute Reset compress end repeat preset counter Address_Counter ! address to $7FF repeat 1024 times ! starting at $000 to $7FF read count Address_Counter compress ! all adrress. execute Data_read compress end repeat execute OEbar_false end unit ! End of test