!!!!    6    0    1  987108169  Ve870                                         

! Device           : 1824c
! Function         : Static RAM 3-state 32 word x 8 bit
! revision         : B.01.00
! safeguard        : med_out_mos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

vector cycle 1000n
receive delay 900n

assign       VCC             to pins           18                ! VDD
assign       GND             to pins           9                 ! VSS

assign       Address_bus     to pins           1,2,3,4,5
assign       Data_bus        to pins           6,7,8,10,11,12,13,14
assign       Data_D0         to pins   14   !AT Added for minimum pin test.
assign       Data_D1         to pins   13   !AT Added for minimum pin test.
assign       Data_D2         to pins   12   !AT Added for minimum pin test.
assign       Data_D3         to pins   11   !AT Added for minimum pin test.
assign       Data_D4         to pins   10   !AT Added for minimum pin test.
assign       Data_D5         to pins   8    !AT Added for minimum pin test.
assign       Data_D6         to pins   7    !AT Added for minimum pin test.
assign       Data_D7         to pins   6    !AT Added for minimum pin test.

assign       Chip_Select_bar to pins           15
assign       Read_bar        to pins           16
assign       Write_bar       to pins           17
assign       DISABLE         to pins           15,16,17

family       TTL

power        VCC, GND

inputs       Address_bus, Chip_Select_bar, Read_bar, Write_bar, DISABLE

bidirectional       Data_bus
bidirectional  Data_D0, Data_D1, Data_D2, Data_D3 !AT Added for min. pin test.
bidirectional  Data_D4, Data_D5, Data_D6, Data_D7 !AT Added for min. pin test.

when     Write_bar   is "0"   inputs   Data_bus
when     Read_bar    is "0"   outputs  Data_bus

when     DISABLE  is "1XX" inactive    Data_bus
when     DISABLE  is "011" inactive    Data_bus
when     DISABLE  is "010" inactive    Data_bus

trace    Data_bus to   Address_bus, Chip_Select_bar
trace    Data_bus to   Read_bar, Write_bar, DISABLE

disable      Data_bus   with   DISABLE    to   "1XX"
disable      Data_bus   with   DISABLE    to   "011"
disable      Data_bus   with   DISABLE    to   "010"


!*****************************************************************************
!*****************************************************************************

vector       Disable_chip
set     Chip_Select_bar      to         "1"
set     Read_bar             to         "1"
set     Write_bar            to         "1"
end vector

vector       Write_enable
set     Chip_Select_bar      to         "0"
set     Read_bar             to         "1"
set     Write_bar            to         "0"
set     Address_bus          to         "kkkkk"
end vector

vector       Read_enable_1
set     Chip_Select_bar      to         "1"
set     Read_bar             to         "0"
set     Write_bar            to         "1"
set     Address_bus          to         "kkkkk"
end vector

vector       Read_enable_2
set     Chip_Select_bar      to         "0"
set     Read_bar             to         "0"
set     Write_bar            to         "1"
set     Address_bus          to         "kkkkk"
end vector

vector       Write_disable
initialize to Disable_chip
drive Data_bus
set     Address_bus          to         "kkkkk"
set     Data_bus             to         "kkkkkkkk"
end vector

vector       Chip_Select_false
drive Data_bus
set     Chip_Select_bar      to         "1"
set     Read_bar             to         "1"
set     Write_bar            to         "0"
set     Address_bus          to         "kkkkk"
set     Data_bus             to         "00000000"
end vector

vector       Write_false
drive Data_bus
set     Chip_Select_bar      to         "0"
set     Read_bar             to         "1"
set     Write_bar            to         "1"
set     Address_bus          to         "kkkkk"
set     Data_bus             to         "00000000"
end vector

vector       Read_bar_Override
drive Data_bus
set     Chip_Select_bar      to         "0"
set     Read_bar             to         "0"
set     Write_bar            to         "0"
set     Address_bus          to         "00000"
set     Data_bus             to         "00000000"
end vector

vector       Address_00000
initialize to Disable_chip
set     Address_bus          to         "00000"
end vector

vector       Address_00001
initialize to Disable_chip
set     Address_bus          to         "00001"
end vector

vector       Address_00011
initialize to Disable_chip
set     Address_bus          to         "00011"
end vector

vector       Address_00111
initialize to Disable_chip
set     Address_bus          to         "00111"
end vector

vector       Address_01111
initialize to Disable_chip
set     Address_bus          to         "01111"
end vector

vector       Address_11111
initialize to Disable_chip
set     Address_bus          to         "11111"
end vector

vector       Address_11110
initialize to Disable_chip
set     Address_bus          to         "11110"
end vector

vector       Address_11100
initialize to Disable_chip
set     Address_bus          to         "11100"
end vector

vector       Address_11000
initialize to Disable_chip
set     Address_bus          to         "11000"
end vector

vector       Data_In_00000000
initialize to Write_enable
drive Data_bus
set     Data_bus             to         "00000000"
end vector

vector       Data_In_00000001
initialize to Write_enable
drive Data_bus
set     Data_bus             to         "00000001"
end vector

vector       Data_In_00000011
initialize to Write_enable
drive Data_bus
set     Data_bus             to         "00000011"
end vector

vector       Data_In_00000111
initialize to Write_enable
drive Data_bus
set     Data_bus             to         "00000111"
end vector

vector       Data_In_00001111
initialize to Write_enable
drive Data_bus
set     Data_bus             to         "00001111"
end vector


vector       Data_In_00011111
initialize to Write_enable
drive Data_bus
set     Data_bus             to         "00011111"
end vector

vector       Data_In_00111111
initialize to Write_enable
drive Data_bus
set     Data_bus             to         "00111111"
end vector

vector       Data_In_01111111
initialize to Write_enable
drive Data_bus
set     Data_bus             to         "01111111"
end vector

vector       Data_In_11111111
initialize to Write_enable
drive Data_bus
set     Data_bus             to         "11111111"
end vector

vector       Data_Out_00000000
initialize to Read_enable_2
receive Data_bus
set     Data_bus             to         "00000000"
end vector

vector       Data_Out_00000001
initialize to Read_enable_2
receive Data_bus
set     Data_bus             to         "00000001"
end vector

vector       Data_Out_00000011
initialize to Read_enable_2
receive Data_bus
set     Data_bus             to         "00000011"
end vector

vector       Data_Out_00000111
initialize to Read_enable_2
receive Data_bus
set     Data_bus             to         "00000111"
end vector

vector       Data_Out_00001111
initialize to Read_enable_2
receive Data_bus
set     Data_bus             to         "00001111"
end vector

vector       Data_Out_00011111
initialize to Read_enable_2
receive Data_bus
set     Data_bus             to         "00011111"
end vector

vector       Data_Out_00111111
initialize to Read_enable_2
receive Data_bus
set     Data_bus             to         "00111111"
end vector

vector       Data_Out_01111111
initialize to Read_enable_2
receive Data_bus
set     Data_bus             to         "01111111"
end vector

vector       Data_Out_11111111
initialize to Read_enable_2
receive Data_bus
set     Data_bus             to         "11111111"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector       Write_disable_D0
initialize to Disable_chip
drive Data_D0
set     Address_bus          to         "kkkkk"
set     Data_D0              to         "k"
end vector

vector       Write_disable_D1
initialize to Disable_chip
drive Data_D1
set     Address_bus          to         "kkkkk"
set     Data_D1              to         "k"
end vector

vector       Write_disable_D2
initialize to Disable_chip
drive Data_D2
set     Address_bus          to         "kkkkk"
set     Data_D2              to         "k"
end vector

vector       Write_disable_D3
initialize to Disable_chip
drive Data_D3
set     Address_bus          to         "kkkkk"
set     Data_D3              to         "k"
end vector

vector       Write_disable_D4
initialize to Disable_chip
drive Data_D4
set     Address_bus          to         "kkkkk"
set     Data_D4              to         "k"
end vector

vector       Write_disable_D5
initialize to Disable_chip
drive Data_D5
set     Address_bus          to         "kkkkk"
set     Data_D5              to         "k"
end vector

vector       Write_disable_D6
initialize to Disable_chip
drive Data_D6
set     Address_bus          to         "kkkkk"
set     Data_D6              to         "k"
end vector

vector       Write_disable_D7
initialize to Disable_chip
drive Data_D7
set     Address_bus          to         "kkkkk"
set     Data_D7              to         "k"
end vector

vector       Data_In_D0_0
initialize to Write_enable
drive Data_D0
set     Data_D0              to         "0"
end vector

vector       Data_In_D0_1
initialize to Write_enable
drive Data_D0
set     Data_D0              to         "1"
end vector

vector       Data_In_D1_0
initialize to Write_enable
drive Data_D1
set     Data_D1              to         "0"
end vector

vector       Data_In_D1_1
initialize to Write_enable
drive Data_D1
set     Data_D1              to         "1"
end vector

vector       Data_In_D2_0
initialize to Write_enable
drive Data_D2
set     Data_D2              to         "0"
end vector

vector       Data_In_D2_1
initialize to Write_enable
drive Data_D2
set     Data_D2              to         "1"
end vector

vector       Data_In_D3_0
initialize to Write_enable
drive Data_D3
set     Data_D3              to         "0"
end vector

vector       Data_In_D3_1
initialize to Write_enable
drive Data_D3
set     Data_D3              to         "1"
end vector

vector       Data_In_D4_0
initialize to Write_enable
drive Data_D4
set     Data_D4              to         "0"
end vector

vector       Data_In_D4_1
initialize to Write_enable
drive Data_D4
set     Data_D4              to         "1"
end vector

vector       Data_In_D5_0
initialize to Write_enable
drive Data_D5
set     Data_D5              to         "0"
end vector

vector       Data_In_D5_1
initialize to Write_enable
drive Data_D5
set     Data_D5              to         "1"
end vector

vector       Data_In_D6_0
initialize to Write_enable
drive Data_D6
set     Data_D6              to         "0"
end vector

vector       Data_In_D6_1
initialize to Write_enable
drive Data_D6
set     Data_D6              to         "1"
end vector

vector       Data_In_D7_0
initialize to Write_enable
drive Data_D7
set     Data_D7              to         "0"
end vector

vector       Data_In_D7_1
initialize to Write_enable
drive Data_D7
set     Data_D7              to         "1"
end vector

vector       Data_Out_D0_0
initialize to Read_enable_2
receive Data_D0
set     Data_D0              to         "0"
end vector

vector       Data_Out_D0_1
initialize to Read_enable_2
receive Data_D0
set     Data_D0              to         "1"
end vector

vector       Data_Out_D1_0
initialize to Read_enable_2
receive Data_D1
set     Data_D1              to         "0"
end vector

vector       Data_Out_D1_1
initialize to Read_enable_2
receive Data_D1
set     Data_D1              to         "1"
end vector

vector       Data_Out_D2_0
initialize to Read_enable_2
receive Data_D2
set     Data_D2              to         "0"
end vector

vector       Data_Out_D2_1
initialize to Read_enable_2
receive Data_D2
set     Data_D2              to         "1"
end vector

vector       Data_Out_D3_0
initialize to Read_enable_2
receive Data_D3
set     Data_D3              to         "0"
end vector

vector       Data_Out_D3_1
initialize to Read_enable_2
receive Data_D3
set     Data_D3              to         "1"
end vector

vector       Data_Out_D4_0
initialize to Read_enable_2
receive Data_D4
set     Data_D4              to         "0"
end vector

vector       Data_Out_D4_1
initialize to Read_enable_2
receive Data_D4
set     Data_D4              to         "1"
end vector

vector       Data_Out_D5_0
initialize to Read_enable_2
receive Data_D5
set     Data_D5              to         "0"
end vector

vector       Data_Out_D5_1
initialize to Read_enable_2
receive Data_D5
set     Data_D5              to         "1"
end vector

vector       Data_Out_D6_0
initialize to Read_enable_2
receive Data_D6
set     Data_D6              to         "0"
end vector

vector       Data_Out_D6_1
initialize to Read_enable_2
receive Data_D6
set     Data_D6              to         "1"
end vector

vector       Data_Out_D7_0
initialize to Read_enable_2
receive Data_D7
set     Data_D7              to         "0"
end vector

vector       Data_Out_D7_1
initialize to Read_enable_2
receive Data_D7
set     Data_D7              to         "1"
end vector

!*****************************************************************************
!*****************************************************************************

!     "Ram_Test" tests I/O pins for proper operation using a graycode pattern
!      for both addresses and data.
!     "Test_Chip_Select_bar" tests for proper operation of the Chip Select pi
!     "Test_Write_bar" tests for proper operation of the MWR_bar pin
!     "Test_Read_bar_Override" tests the MRD_bar pin to insure that it over-
!      rides the MWR_bar_true state



sub          Write_Data (Address,Data)
execute              Address
execute              Data
execute              Write_Disable
end sub

sub          Read_Data (Address,Data)
execute              Address
execute              Read_enable_1
execute              Data
end sub

!AT The following subroutines have been added for a minimum pins test.
!AT Vectors in the subroutine "Write_data" reference the entire data bus.
!AT Therefore this subroutine was copied and modified to reference only
!AT a single pin of the data bus. The subroutine "Read_data" did not
!AT require any modification as all references to the data bus are made
!AT via a passed parameter (data). This reference can be modified in the
!AT call statement.

sub  Write_data_Dx (Address, Data_Dx, Write_Disable_Dx)
execute              Address
execute              Data_Dx
execute              Write_Disable_Dx
end sub

!*****************************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit   "awaretest D0 Test"

call           Write_Data_Dx (Address_00000,Data_In_D0_0, Write_Disable_D0)
call           Read_Data (Address_00000,Data_Out_D0_0)

call           Write_Data_Dx (Address_00000,Data_In_D0_1, Write_Disable_D0)
call           Read_Data (Address_00000,Data_Out_D0_1)

end unit

unit   "awaretest D1 Test"

call           Write_Data_Dx (Address_00000,Data_In_D1_0, Write_Disable_D1)
call           Read_Data (Address_00000,Data_Out_D1_0)

call           Write_Data_Dx (Address_00000,Data_In_D1_1, Write_Disable_D1)
call           Read_Data (Address_00000,Data_Out_D1_1)

end unit

unit   "awaretest D2 Test"

call           Write_Data_Dx (Address_00000,Data_In_D2_0, Write_Disable_D2)
call           Read_Data (Address_00000,Data_Out_D2_0)

call           Write_Data_Dx (Address_00000,Data_In_D2_1, Write_Disable_D2)
call           Read_Data (Address_00000,Data_Out_D2_1)

end unit

unit   "awaretest D3 Test"

call           Write_Data_Dx (Address_00000,Data_In_D3_0, Write_Disable_D3)
call           Read_Data (Address_00000,Data_Out_D3_0)

call           Write_Data_Dx (Address_00000,Data_In_D3_1, Write_Disable_D3)
call           Read_Data (Address_00000,Data_Out_D3_1)

end unit

unit   "awaretest D4 Test"

call           Write_Data_Dx (Address_00000,Data_In_D4_0, Write_Disable_D4)
call           Read_Data (Address_00000,Data_Out_D4_0)

call           Write_Data_Dx (Address_00000,Data_In_D4_1, Write_Disable_D4)
call           Read_Data (Address_00000,Data_Out_D4_1)

end unit

unit   "awaretest D5 Test"

call           Write_Data_Dx (Address_00000,Data_In_D5_0, Write_Disable_D5)
call           Read_Data (Address_00000,Data_Out_D5_0)

call           Write_Data_Dx (Address_00000,Data_In_D5_1, Write_Disable_D5)
call           Read_Data (Address_00000,Data_Out_D5_1)

end unit

unit   "awaretest D6 Test"

call           Write_Data_Dx (Address_00000,Data_In_D6_0, Write_Disable_D6)
call           Read_Data (Address_00000,Data_Out_D6_0)

call           Write_Data_Dx (Address_00000,Data_In_D6_1, Write_Disable_D6)
call           Read_Data (Address_00000,Data_Out_D6_1)

end unit

unit   "awaretest D7 Test"

call           Write_Data_Dx (Address_00000,Data_In_D7_0, Write_Disable_D7)
call           Read_Data (Address_00000,Data_Out_D7_0)

call           Write_Data_Dx (Address_00000,Data_In_D7_1, Write_Disable_D7)
call           Read_Data (Address_00000,Data_Out_D7_1)

end unit

unit    "Ram_Test"
call           Write_Data (Address_00000,Data_In_00000000)
call           Write_Data (Address_00001,Data_In_00000001)
call           Write_Data (Address_00011,Data_In_00000011)
call           Write_Data (Address_00111,Data_In_00000111)
call           Write_Data (Address_01111,Data_In_00001111)
call           Write_Data (Address_11111,Data_In_00011111)
call           Write_Data (Address_11110,Data_In_00111111)
call           Write_Data (Address_11100,Data_In_01111111)
call           Write_Data (Address_11000,Data_In_11111111)
call           Read_Data (Address_00000,Data_Out_00000000)
call           Read_Data (Address_00001,Data_Out_00000001)
call           Read_Data (Address_00011,Data_Out_00000011)
call           Read_Data (Address_00111,Data_Out_00000111)
call           Read_Data (Address_01111,Data_Out_00001111)
call           Read_Data (Address_11111,Data_Out_00011111)
call           Read_Data (Address_11110,Data_Out_00111111)
call           Read_Data (Address_11100,Data_Out_01111111)
call           Read_Data (Address_11000,Data_Out_11111111)
end unit

unit      "Test_Chip_Select_bar"
call           Write_Data (Address_00000,Data_In_11111111)
execute        Address_00000
execute        Chip_Select_false
execute        Write_Disable
call           Read_Data (Address_00000,Data_Out_11111111)
end unit

unit     "Test_Write_bar"
call           Write_Data (Address_00000,Data_In_11111111)
execute        Address_00000
execute        Write_false
execute        Write_Disable
call           Read_Data (Address_00000,Data_Out_11111111)
end unit

unit     "Test_Read_bar_Override"
call           Write_Data (Address_00000,Data_In_11111111)
execute        Address_00000
execute        Read_bar_Override
execute        Write_Disable
call           Read_Data (Address_00000,Data_Out_11111111)
end unit


!     End of test