!!!!    6    0    1  987108134  Vaeb0                                         

! Device           : 1823c
! Function         : Static RAM 3-state 128 x 8
! revision         : B.01.00
! safeguard        : med_out_mos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

assign    VCC            to pins   24                          !  VDD
assign    GND            to pins   12                          !  VSS

assign    Address        to pins   17,18,19,20,21,22,23

assign    Data           to pins   8,7,6,5,4,3,2,1
assign    Data_D0        to pins   1    !AT Added for minimum pin test.
assign    Data_D1        to pins   2    !AT Added for minimum pin test.
assign    Data_D2        to pins   3    !AT Added for minimum pin test.
assign    Data_D3        to pins   4    !AT Added for minimum pin test.
assign    Data_D4        to pins   5    !AT Added for minimum pin test.
assign    Data_D5        to pins   6    !AT Added for minimum pin test.
assign    Data_D6        to pins   7    !AT Added for minimum pin test.
assign    Data_D7        to pins   8    !AT Added for minimum pin test.

assign    Chip_select_1         to pins   9
assign    Chip_select_4         to pins   13
assign    Chip_select_2_bar     to pins   10
assign    Chip_select_3_bar     to pins   11
assign    Chip_select_5_bar     to pins   14
assign    Chip_selects          to pins   9,10,11,13,14    !  CS_1_2_3_4_5

assign    Write_bar             to pins   16
assign    Read_bar              to pins   15

family    TTL

power     VCC, GND

inputs    Address, Write_bar, Read_bar
inputs    Chip_selects, Chip_select_1, Chip_select_4
inputs    Chip_select_2_bar, Chip_select_3_bar
inputs    Chip_select_5_bar

bidirectional  Data
bidirectional  Data_D0, Data_D1, Data_D2, Data_D3 !AT Added for min. pin test.
bidirectional  Data_D4, Data_D5, Data_D6, Data_D7 !AT Added for min. pin test.

when   Write_bar  is "0"   inputs   Data
when   Read_bar   is "0"   outputs  Data

when   Chip_select_1     is "0"  inactive    Data
when   Chip_select_2_bar is "1"  inactive    Data
when   Chip_select_3_bar is "1"  inactive    Data
when   Chip_select_4     is "0"  inactive    Data
when   Chip_select_5_bar is "1"  inactive    Data

trace Data to  Address, Write_bar, Read_bar
trace Data to  Chip_selects, Chip_select_1, Chip_select_4
trace Data to  Chip_select_2_bar, Chip_select_3_bar
trace Data to  Chip_select_5_bar

disable   Data      with Chip_select_1         to   "0"
disable   Data      with Chip_select_2_bar     to   "1"
disable   Data      with Chip_select_3_bar     to   "1"
disable   Data      with Chip_select_4         to   "0"
disable   Data      with Chip_select_5_bar     to   "1"

!***************************************************************
!***************************************************************

vector    Disable
     set  Read_bar            to   "1"
     set  Write_bar           to   "1"
     set  Chip_selects        to   "01101"
end vector

vector    Chip_selects_true
     set  Address             to   "kkkkkkk"
     set  Write_bar           to   "1"
     set  Read_bar            to   "1"
     set  Chip_selects        to   "10010"
end vector

vector    Write_true
     set  Address             to   "kkkkkkk"
     set  Write_bar           to   "0"
     set  Read_bar            to   "1"
     set  Chip_selects        to   "kkkkk"
end vector

vector    Write_false
     drive Data
     set  Address             to   "kkkkkkk"
     set  Data                to   "kkkkkkkk"
     set  Write_bar           to   "1"
     set  Read_bar            to   "1"
     set  Chip_selects        to   "kkkkk"
end vector

vector    Chip_Select_1_false
     set  Address             to   "kkkkkkk"
     set  Write_bar           to   "0"
     set  Read_bar            to   "1"
     set  Chip_selects        to   "00010"
end vector

vector    Chip_Select_2_false
     set  Address             to   "kkkkkkk"
     set  Write_bar           to   "0"
     set  Read_bar            to   "1"
     set  Chip_selects        to   "11010"
end vector

vector    Chip_Select_3_false
     set  Address             to   "kkkkkkk"
     set  Write_bar           to   "0"
     set  Read_bar            to   "1"
     set  Chip_selects        to   "10110"
end vector

vector    Chip_Select_4_false
     set  Address             to   "kkkkkkk"
     set  Write_bar           to   "0"
     set  Read_bar            to   "1"
     set  Chip_selects        to   "10000"
end vector

vector    Chip_Select_5_false
     set  Address             to   "kkkkkkk"
     set  Write_bar           to   "0"
     set  Read_bar            to   "1"
     set  Chip_selects        to   "10011"
end vector

vector    Read_true
     set  Address             to   "kkkkkkk"
     set  Write_bar           to   "1"
     set  Read_bar            to   "0"
     set  Chip_selects        to   "10010"
end vector

vector    Address_0000000
     initialize to  Disable
     set  Address   to   "0000000"
end vector

vector    Address_0000001
     initialize to  Disable
     set  Address   to   "0000001"
end vector

vector    Address_0000011
     initialize to  Disable
     set  Address   to   "0000011"
end vector

vector    Address_0000111
     initialize to  Disable
     set  Address   to   "0000111"
end vector

vector    Address_0001111
     initialize to  Disable
     set  Address   to   "0001111"
end vector

vector    Address_0011111
     initialize to  Disable
     set  Address   to   "0011111"
end vector

vector    Address_0111111
     initialize to  Disable
     set  Address   to   "0111111"
end vector

vector    Address_1111111
     initialize to  Disable
     set  Address   to   "1111111"
end vector

vector    Address_1111110
     initialize to  Disable
     set  Address   to   "1111110"
end vector

vector    Data_write_00000000_W_false
     drive  Data
     set Address      to   "kkkkkkk"
     set Write_bar    to   "1"
     set Read_bar     to   "1"
     set Chip_selects to   "kkkkk"
     set Data         to   "00000000"
end vector

vector    Data_write_00000000
     initialize to  Write_true
     drive Data
     set Data       to   "00000000"
end vector

vector    Data_write_00000001
     initialize to  Write_true
     drive Data
     set Data       to   "00000001"
end vector

vector    Data_write_00000011
     initialize to  Write_true
     drive Data
     set Data       to   "00000011"
end vector

vector    Data_write_00000111
     initialize to  Write_true
     drive Data
     set Data       to   "00000111"
end vector

vector    Data_write_00001111
     initialize to  Write_true
     drive Data
     set Data       to   "00001111"
end vector

vector    Data_write_00011111
     initialize to  Write_true
     drive Data
     set Data       to   "00011111"
end vector

vector    Data_write_00111111
     initialize to  Write_true
     drive Data
     set Data       to   "00111111"
end vector

vector    Data_write_01111111
     initialize to  Write_true
     drive Data
     set Data       to   "01111111"
end vector

vector    Data_write_11111111
     initialize to  Write_true
     drive Data
     set Data       to   "11111111"
end vector

vector    Data_read_00000000
     initialize to  Read_true
     receive   Data
     set Data       to   "00000000"
end vector

vector    Data_read_00000001
     initialize to  Read_true
     receive   Data
     set Data       to   "00000001"
end vector

vector    Data_read_00000011
     initialize to  Read_true
     receive   Data
     set Data       to   "00000011"
end vector

vector    Data_read_00000111
     initialize to  Read_true
     receive   Data
     set Data       to   "00000111"
end vector

vector    Data_read_00001111
     initialize to  Read_true
     receive   Data
     set Data       to   "00001111"
end vector

vector    Data_read_00011111
     initialize to  Read_true
     receive   Data
     set Data       to   "00011111"
end vector

vector    Data_read_00111111
     initialize to  Read_true
     receive   Data
     set Data       to   "00111111"
end vector

vector    Data_read_01111111
     initialize to  Read_true
     receive   Data
     set Data       to   "01111111"
end vector

vector    Data_read_11111111
     initialize to  Read_true
     receive   Data
     set Data       to   "11111111"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector    Write_false_D0
     drive Data_D0
     set  Address             to   "kkkkkkk"
     set  Data_D0             to   "k"
     set  Write_bar           to   "1"
     set  Read_bar            to   "1"
     set  Chip_selects        to   "kkkkk"
end vector

vector    Write_false_D1
     drive Data_D1
     set  Address             to   "kkkkkkk"
     set  Data_D1             to   "k"
     set  Write_bar           to   "1"
     set  Read_bar            to   "1"
     set  Chip_selects        to   "kkkkk"
end vector

vector    Write_false_D2
     drive Data_D2
     set  Address             to   "kkkkkkk"
     set  Data_D2             to   "k"
     set  Write_bar           to   "1"
     set  Read_bar            to   "1"
     set  Chip_selects        to   "kkkkk"
end vector

vector    Write_false_D3
     drive Data_D3
     set  Address             to   "kkkkkkk"
     set  Data_D3             to   "k"
     set  Write_bar           to   "1"
     set  Read_bar            to   "1"
     set  Chip_selects        to   "kkkkk"
end vector

vector    Write_false_D4
     drive Data_D4
     set  Address             to   "kkkkkkk"
     set  Data_D4             to   "k"
     set  Write_bar           to   "1"
     set  Read_bar            to   "1"
     set  Chip_selects        to   "kkkkk"
end vector

vector    Write_false_D5
     drive Data_D5
     set  Address             to   "kkkkkkk"
     set  Data_D5             to   "k"
     set  Write_bar           to   "1"
     set  Read_bar            to   "1"
     set  Chip_selects        to   "kkkkk"
end vector

vector    Write_false_D6
     drive Data_D6
     set  Address             to   "kkkkkkk"
     set  Data_D6             to   "k"
     set  Write_bar           to   "1"
     set  Read_bar            to   "1"
     set  Chip_selects        to   "kkkkk"
end vector

vector    Write_false_D7
     drive Data_D7
     set  Address             to   "kkkkkkk"
     set  Data_D7             to   "k"
     set  Write_bar           to   "1"
     set  Read_bar            to   "1"
     set  Chip_selects        to   "kkkkk"
end vector

vector    Data_write_D0_0
     initialize to  Write_true
     drive Data_D0
     set Data_D0    to   "0"
end vector

vector    Data_write_D0_1
     initialize to  Write_true
     drive Data_D0
     set Data_D0    to   "1"
end vector

vector    Data_write_D1_0
     initialize to  Write_true
     drive Data_D1
     set Data_D1    to   "0"
end vector

vector    Data_write_D1_1
     initialize to  Write_true
     drive Data_D1
     set Data_D1    to   "1"
end vector

vector    Data_write_D2_0
     initialize to  Write_true
     drive Data_D2
     set Data_D2    to   "0"
end vector

vector    Data_write_D2_1
     initialize to  Write_true
     drive Data_D2
     set Data_D2    to   "1"
end vector

vector    Data_write_D3_0
     initialize to  Write_true
     drive Data_D3
     set Data_D3    to   "0"
end vector

vector    Data_write_D3_1
     initialize to  Write_true
     drive Data_D3
     set Data_D3    to   "1"
end vector

vector    Data_write_D4_0
     initialize to  Write_true
     drive Data_D4
     set Data_D4    to   "0"
end vector

vector    Data_write_D4_1
     initialize to  Write_true
     drive Data_D4
     set Data_D4    to   "1"
end vector

vector    Data_write_D5_0
     initialize to  Write_true
     drive Data_D5
     set Data_D5    to   "0"
end vector

vector    Data_write_D5_1
     initialize to  Write_true
     drive Data_D5
     set Data_D5    to   "1"
end vector

vector    Data_write_D6_0
     initialize to  Write_true
     drive Data_D6
     set Data_D6    to   "0"
end vector

vector    Data_write_D6_1
     initialize to  Write_true
     drive Data_D6
     set Data_D6    to   "1"
end vector

vector    Data_write_D7_0
     initialize to  Write_true
     drive Data_D7
     set Data_D7    to   "0"
end vector

vector    Data_write_D7_1
     initialize to  Write_true
     drive Data_D7
     set Data_D7    to   "1"
end vector

vector    Data_read_D0_0
     initialize to  Read_true
     receive   Data_D0
     set Data_D0    to   "0"
end vector

vector    Data_read_D0_1
     initialize to  Read_true
     receive   Data_D0
     set Data_D0    to   "1"
end vector

vector    Data_read_D1_0
     initialize to  Read_true
     receive   Data_D1
     set Data_D1    to   "0"
end vector

vector    Data_read_D1_1
     initialize to  Read_true
     receive   Data_D1
     set Data_D1    to   "1"
end vector

vector    Data_read_D2_0
     initialize to  Read_true
     receive   Data_D2
     set Data_D2    to   "0"
end vector

vector    Data_read_D2_1
     initialize to  Read_true
     receive   Data_D2
     set Data_D2    to   "1"
end vector

vector    Data_read_D3_0
     initialize to  Read_true
     receive   Data_D3
     set Data_D3    to   "0"
end vector

vector    Data_read_D3_1
     initialize to  Read_true
     receive   Data_D3
     set Data_D3    to   "1"
end vector

vector    Data_read_D4_0
     initialize to  Read_true
     receive   Data_D4
     set Data_D4    to   "0"
end vector

vector    Data_read_D4_1
     initialize to  Read_true
     receive   Data_D4
     set Data_D4    to   "1"
end vector

vector    Data_read_D5_0
     initialize to  Read_true
     receive   Data_D5
     set Data_D5    to   "0"
end vector

vector    Data_read_D5_1
     initialize to  Read_true
     receive   Data_D5
     set Data_D5    to   "1"
end vector

vector    Data_read_D6_0
     initialize to  Read_true
     receive   Data_D6
     set Data_D6    to   "0"
end vector

vector    Data_read_D6_1
     initialize to  Read_true
     receive   Data_D6
     set Data_D6    to   "1"
end vector

vector    Data_read_D7_0
     initialize to  Read_true
     receive   Data_D7
     set Data_D7    to   "0"
end vector

vector    Data_read_D7_1
     initialize to  Read_true
     receive   Data_D7
     set Data_D7    to   "1"
end vector

!*****************************************************************************
!*****************************************************************************

sub  Write_data (Address, Data)
     execute   Address
     execute   Chip_selects_true
     execute   Write_true
     execute   Data
     execute   Write_false
end sub

sub  Read_data (Address, Data)
     execute   Address
     execute   Read_true
     execute   Data
end sub

!AT The following subroutines have been added for a minimum pins test.
!AT Vectors in the subroutine "Write_data" reference the entire data bus.
!AT Therefore this subroutine was copied and modified to reference only
!AT a single pin of the data bus. The subroutine "Read_data" did not
!AT require any modification as all references to the data bus are made
!AT via a passed parameter (data). This reference can be modified in the
!AT call statement.

sub  Write_data_Dx (Address, Data_Dx, Write_false_Dx)
     execute   Address
     execute   Chip_selects_true
     execute   Write_true
     execute   Data_Dx
     execute   Write_false_Dx
end sub

!*****************************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit   "awaretest D0 Test"

     call Write_data_Dx (Address_0000000, Data_write_D0_0, Write_false_D0)
     call Read_data (Address_0000000, Data_read_D0_0)

     call Write_data_Dx (Address_0000000, Data_write_D0_1, Write_false_D0)
     call Read_data (Address_0000000, Data_read_D0_1)

end unit

unit   "awaretest D1 Test"

     call Write_data_Dx (Address_0000000, Data_write_D1_0, Write_false_D1)
     call Read_data (Address_0000000, Data_read_D1_0)

     call Write_data_Dx (Address_0000000, Data_write_D1_1, Write_false_D1)
     call Read_data (Address_0000000, Data_read_D1_1)

end unit

unit   "awaretest D2 Test"

     call Write_data_Dx (Address_0000000, Data_write_D2_0, Write_false_D2)
     call Read_data (Address_0000000, Data_read_D2_0)

     call Write_data_Dx (Address_0000000, Data_write_D2_1, Write_false_D2)
     call Read_data (Address_0000000, Data_read_D2_1)

end unit

unit   "awaretest D3 Test"

     call Write_data_Dx (Address_0000000, Data_write_D3_0, Write_false_D3)
     call Read_data (Address_0000000, Data_read_D3_0)

     call Write_data_Dx (Address_0000000, Data_write_D3_1, Write_false_D3)
     call Read_data (Address_0000000, Data_read_D3_1)

end unit

unit   "awaretest D4 Test"

     call Write_data_Dx (Address_0000000, Data_write_D4_0, Write_false_D4)
     call Read_data (Address_0000000, Data_read_D4_0)

     call Write_data_Dx (Address_0000000, Data_write_D4_1, Write_false_D4)
     call Read_data (Address_0000000, Data_read_D4_1)

end unit

unit   "awaretest D5 Test"

     call Write_data_Dx (Address_0000000, Data_write_D5_0, Write_false_D5)
     call Read_data (Address_0000000, Data_read_D5_0)

     call Write_data_Dx (Address_0000000, Data_write_D5_1, Write_false_D5)
     call Read_data (Address_0000000, Data_read_D5_1)

end unit

unit   "awaretest D6 Test"

     call Write_data_Dx (Address_0000000, Data_write_D6_0, Write_false_D6)
     call Read_data (Address_0000000, Data_read_D6_0)

     call Write_data_Dx (Address_0000000, Data_write_D6_1, Write_false_D6)
     call Read_data (Address_0000000, Data_read_D6_1)

end unit

unit   "awaretest D7 Test"

     call Write_data_Dx (Address_0000000, Data_write_D7_0, Write_false_D7)
     call Read_data (Address_0000000, Data_read_D7_0)

     call Write_data_Dx (Address_0000000, Data_write_D7_1, Write_false_D7)
     call Read_data (Address_0000000, Data_read_D7_1)

end unit

unit "RAM test"
     call Write_data (Address_0000000, Data_write_00000000)
     call Write_data (Address_0000001, Data_write_00000001)
     call Write_data (Address_0000011, Data_write_00000011)
     call Write_data (Address_0000111, Data_write_00000111)
     call Write_data (Address_0001111, Data_write_00001111)
     call Write_data (Address_0011111, Data_write_00011111)
     call Write_data (Address_0111111, Data_write_00111111)
     call Write_data (Address_1111111, Data_write_01111111)
     call Write_data (Address_1111110, Data_write_11111111)
     call Read_data (Address_0000000, Data_read_00000000)
     call Read_data (Address_0000011, Data_read_00000001)
     call Read_data (Address_0000011, Data_read_00000011)
     call Read_data (Address_0000111, Data_read_00000111)
     call Read_data (Address_0001111, Data_read_00001111)
     call Read_data (Address_0011111, Data_read_00011111)
     call Read_data (Address_0111111, Data_read_00111111)
     call Read_data (Address_1111111, Data_read_01111111)
     call Read_data (Address_1111110, Data_read_11111111)
     execute   Disable
end unit

unit "Test Chip_select_1"
     call Write_data (Address_0000000, Data_write_11111111)
     execute Address_0000000
     execute Chip_select_1_false
     execute Data_write_00000000
     execute Write_false
     call Read_data (Address_0000000, Data_read_11111111)
end unit

unit "Test Chip_select_2"
     call Write_data (Address_0000000, Data_write_11111111)
     execute Address_0000000
     execute Chip_select_2_false
     execute Data_write_00000000
     execute Write_false
     call Read_data (Address_0000000, Data_read_11111111)
end unit

unit "Test Chip_select_3"
     call Write_data (Address_0000000, Data_write_11111111)
     execute Address_0000000
     execute Chip_select_3_false
     execute Data_write_00000000
     execute Write_false
     call Read_data (Address_0000000, Data_read_11111111)
end unit

unit "Test Chip_select_4"
     call Write_data (Address_0000000, Data_write_11111111)
     execute Address_0000000
     execute Chip_select_4_false
     execute Data_write_00000000
     execute Write_false
     call Read_data (Address_0000000, Data_read_11111111)
end unit

unit "Test Chip_select_5"
     call Write_data (Address_0000000, Data_write_11111111)
     execute Address_0000000
     execute Chip_select_5_false
     execute Data_write_00000000
     execute Write_false
     call Read_data (Address_0000000, Data_read_11111111)
end unit

unit "Test Write_bar"
     call Write_data (Address_0000000, Data_write_11111111)
     execute Address_0000000
     execute Chip_selects_true
     execute Data_write_00000000_W_false
     execute Write_false
     call Read_data (Address_0000000, Data_read_11111111)
end unit