!!!! 6 0 1 986331151 Vf7f2 ! Device : 100422 ! Function : RAM 1k 256 x 4 ! revision : B.01.00 ! safeguard : 100k_ecl ! Modifications : Modified for AwareTest xi ! warning "This library has not been verified with hardware." assign VCC1 to pins 10 assign VCC2 to pins 9 assign VEE to pins 21 assign Block_select_bar to pins 7,5,14,12 assign Write_enable_bar to pins 17 assign Data_inputs to pins 4,3,16,15 assign Address to pins 20,19,18,2,1,24,23,22 assign Data_outputs to pins 8,6,13,11 assign Data_in_D0 to pins 15 !AT Added for minimum pin test. assign Data_in_D1 to pins 16 !AT Added for minimum pin test. assign Data_in_D2 to pins 3 !AT Added for minimum pin test. assign Data_in_D3 to pins 4 !AT Added for minimum pin test. assign Data_out_D0 to pins 11 !AT Added for minimum pin test. assign Data_out_D1 to pins 13 !AT Added for minimum pin test. assign Data_out_D2 to pins 6 !AT Added for minimum pin test. assign Data_out_D3 to pins 8 !AT Added for minimum pin test. family ECL power VCC1, VCC2, VEE inputs Block_select_bar, Write_enable_bar, Data_inputs, Address inputs Data_in_D0, Data_in_D1, Data_in_D2, Data_in_D3 !AT Added for minimum pin test. outputs Data_outputs outputs Data_out_D0, Data_out_D1, Data_out_D2, Data_out_D3 !AT Added for minimum pin test. disable Data_outputs with Block_select_bar to "1111" trace Data_outputs to Block_select_bar, Write_enable_bar trace Data_outputs to Data_inputs, Address !************************************************************************* !************************************************************************* vector Block_select_true set Block_select_bar to "0000" set Write_enable_bar to "1" end vector vector Block_select_false set Block_select_bar to "1111" set Write_enable_bar to "1" end vector vector Write_true set Block_select_bar to "kkkk" set Data_inputs to "kkkk" set Address to "kkkkkkkk" set Write_enable_bar to "0" end vector vector Write_false set Block_select_bar to "kkkk" set Data_inputs to "kkkk" set Address to "kkkkkkkk" set Write_enable_bar to "1" end vector vector Out_Address_00000000 set Block_select_bar to "kkkk" set Address to "00000000" set Write_enable_bar to "k" end vector vector Out_Address_00000001 set Block_select_bar to "kkkk" set Address to "00000001" set Write_enable_bar to "k" end vector vector Out_Address_00000011 set Block_select_bar to "kkkk" set Address to "00000011" set Write_enable_bar to "k" end vector vector Out_Address_00000111 set Block_select_bar to "kkkk" set Address to "00000111" set Write_enable_bar to "k" end vector vector Out_Address_00001111 set Block_select_bar to "kkkk" set Address to "00001111" set Write_enable_bar to "k" end vector vector Out_Address_00011111 set Block_select_bar to "kkkk" set Address to "00011111" set Write_enable_bar to "k" end vector vector Out_Address_00111111 set Block_select_bar to "kkkk" set Address to "00111111" set Write_enable_bar to "k" end vector vector Out_Address_01111111 set Block_select_bar to "kkkk" set Address to "01111111" set Write_enable_bar to "k" end vector vector Out_Address_11111111 set Block_select_bar to "kkkk" set Address to "11111111" set Write_enable_bar to "k" end vector vector In_Address_00000000 set Block_select_bar to "kkkk" set Data_inputs to "kkkk" set Address to "00000000" set Write_enable_bar to "k" end vector vector In_Address_00000001 set Block_select_bar to "kkkk" set Data_inputs to "kkkk" set Address to "00000001" set Write_enable_bar to "k" end vector vector In_Address_00000011 set Block_select_bar to "kkkk" set Data_inputs to "kkkk" set Address to "00000011" set Write_enable_bar to "k" end vector vector In_Address_00000111 set Block_select_bar to "kkkk" set Data_inputs to "kkkk" set Address to "00000111" set Write_enable_bar to "k" end vector vector In_Address_00001111 set Block_select_bar to "kkkk" set Data_inputs to "kkkk" set Address to "00001111" set Write_enable_bar to "k" end vector vector In_Address_00011111 set Block_select_bar to "kkkk" set Data_inputs to "kkkk" set Address to "00011111" set Write_enable_bar to "k" end vector vector In_Address_00111111 set Block_select_bar to "kkkk" set Data_inputs to "kkkk" set Address to "00111111" set Write_enable_bar to "k" end vector vector In_Address_01111111 set Block_select_bar to "kkkk" set Data_inputs to "kkkk" set Address to "01111111" set Write_enable_bar to "k" end vector vector In_Address_11111111 set Block_select_bar to "kkkk" set Data_inputs to "kkkk" set Address to "11111111" set Write_enable_bar to "k" end vector vector Data_in_0000 set Block_select_bar to "kkkk" set Data_inputs to "0000" set Write_enable_bar to "k" end vector vector Data_in_0001 set Block_select_bar to "kkkk" set Data_inputs to "0001" set Write_enable_bar to "k" end vector vector Data_in_0011 set Block_select_bar to "kkkk" set Data_inputs to "0011" set Write_enable_bar to "k" end vector vector Data_in_0111 set Block_select_bar to "kkkk" set Data_inputs to "0111" set Write_enable_bar to "k" end vector vector Data_in_1111 set Block_select_bar to "kkkk" set Data_inputs to "1111" set Write_enable_bar to "k" end vector vector Data_in_1110 set Block_select_bar to "kkkk" set Data_inputs to "1110" set Write_enable_bar to "k" end vector vector Data_in_1100 set Block_select_bar to "kkkk" set Data_inputs to "1100" set Write_enable_bar to "k" end vector vector Data_in_1000 set Block_select_bar to "kkkk" set Data_inputs to "1000" set Write_enable_bar to "k" end vector vector Data_in_1001 set Block_select_bar to "kkkk" set Data_inputs to "1001" set Write_enable_bar to "k" end vector vector Data_out_0000 set Block_select_bar to "kkkk" set Address to "kkkkkkkk" set Data_outputs to "0000" set Write_enable_bar to "k" end vector vector Data_out_0001 set Block_select_bar to "kkkk" set Address to "kkkkkkkk" set Data_outputs to "0001" set Write_enable_bar to "k" end vector vector Data_out_0011 set Block_select_bar to "kkkk" set Address to "kkkkkkkk" set Data_outputs to "0011" set Write_enable_bar to "k" end vector vector Data_out_0111 set Block_select_bar to "kkkk" set Address to "kkkkkkkk" set Data_outputs to "0111" set Write_enable_bar to "k" end vector vector Data_out_1111 set Block_select_bar to "kkkk" set Address to "kkkkkkkk" set Data_outputs to "1111" set Write_enable_bar to "k" end vector vector Data_out_1110 set Block_select_bar to "kkkk" set Address to "kkkkkkkk" set Data_outputs to "1110" set Write_enable_bar to "k" end vector vector Data_out_1100 set Block_select_bar to "kkkk" set Address to "kkkkkkkk" set Data_outputs to "1100" set Write_enable_bar to "k" end vector vector Data_out_1000 set Block_select_bar to "kkkk" set Address to "kkkkkkkk" set Data_outputs to "1000" set Write_enable_bar to "k" end vector vector Data_out_1001 set Block_select_bar to "kkkk" set Address to "kkkkkkkk" set Data_outputs to "1001" set Write_enable_bar to "k" end vector !AT The following vectors have been added for a minimum pins test. Any !AT vectors that references the data bus was copied and modified to reference !AT only a single pin of the data bus. vector W_true_D0 set Block_select_bar to "kkkk" set Data_in_D0 to "k" set Address to "kkkkkkkk" set Write_enable_bar to "0" end vector vector W_false_D0 set Block_select_bar to "kkkk" set Data_in_D0 to "k" set Address to "kkkkkkkk" set Write_enable_bar to "1" end vector vector W_true_D1 set Block_select_bar to "kkkk" set Data_in_D1 to "k" set Address to "kkkkkkkk" set Write_enable_bar to "0" end vector vector W_false_D1 set Block_select_bar to "kkkk" set Data_in_D1 to "k" set Address to "kkkkkkkk" set Write_enable_bar to "1" end vector vector W_true_D2 set Block_select_bar to "kkkk" set Data_in_D2 to "k" set Address to "kkkkkkkk" set Write_enable_bar to "0" end vector vector W_false_D2 set Block_select_bar to "kkkk" set Data_in_D2 to "k" set Address to "kkkkkkkk" set Write_enable_bar to "1" end vector vector W_true_D3 set Block_select_bar to "kkkk" set Data_in_D3 to "k" set Address to "kkkkkkkk" set Write_enable_bar to "0" end vector vector W_false_D3 set Block_select_bar to "kkkk" set Data_in_D3 to "k" set Address to "kkkkkkkk" set Write_enable_bar to "1" end vector vector In_Address_0_D0 set Block_select_bar to "kkkk" set Data_in_D0 to "k" set Address to "00000000" set Write_enable_bar to "k" end vector vector In_Address_0_D1 set Block_select_bar to "kkkk" set Data_in_D1 to "k" set Address to "00000000" set Write_enable_bar to "k" end vector vector In_Address_0_D2 set Block_select_bar to "kkkk" set Data_in_D2 to "k" set Address to "00000000" set Write_enable_bar to "k" end vector vector In_Address_0_D3 set Block_select_bar to "kkkk" set Data_in_D3 to "k" set Address to "00000000" set Write_enable_bar to "k" end vector vector Data_in_D0_0 set Block_select_bar to "kkkk" set Data_in_D0 to "0" set Write_enable_bar to "k" end vector vector Data_in_D0_1 set Block_select_bar to "kkkk" set Data_in_D0 to "1" set Write_enable_bar to "k" end vector vector Data_in_D1_0 set Block_select_bar to "kkkk" set Data_in_D1 to "0" set Write_enable_bar to "k" end vector vector Data_in_D1_1 set Block_select_bar to "kkkk" set Data_in_D1 to "1" set Write_enable_bar to "k" end vector vector Data_in_D2_0 set Block_select_bar to "kkkk" set Data_in_D2 to "0" set Write_enable_bar to "k" end vector vector Data_in_D2_1 set Block_select_bar to "kkkk" set Data_in_D2 to "1" set Write_enable_bar to "k" end vector vector Data_in_D3_0 set Block_select_bar to "kkkk" set Data_in_D3 to "0" set Write_enable_bar to "k" end vector vector Data_in_D3_1 set Block_select_bar to "kkkk" set Data_in_D3 to "1" set Write_enable_bar to "k" end vector vector Data_out_D0_0 set Block_select_bar to "kkkk" set Address to "kkkkkkkk" set Data_out_D0 to "0" set Write_enable_bar to "k" end vector vector Data_out_D0_1 set Block_select_bar to "kkkk" set Address to "kkkkkkkk" set Data_out_D0 to "1" set Write_enable_bar to "k" end vector vector Data_out_D1_0 set Block_select_bar to "kkkk" set Address to "kkkkkkkk" set Data_out_D1 to "0" set Write_enable_bar to "k" end vector vector Data_out_D1_1 set Block_select_bar to "kkkk" set Address to "kkkkkkkk" set Data_out_D1 to "1" set Write_enable_bar to "k" end vector vector Data_out_D2_0 set Block_select_bar to "kkkk" set Address to "kkkkkkkk" set Data_out_D2 to "0" set Write_enable_bar to "k" end vector vector Data_out_D2_1 set Block_select_bar to "kkkk" set Address to "kkkkkkkk" set Data_out_D2 to "1" set Write_enable_bar to "k" end vector vector Data_out_D3_0 set Block_select_bar to "kkkk" set Address to "kkkkkkkk" set Data_out_D3 to "0" set Write_enable_bar to "k" end vector vector Data_out_D3_1 set Block_select_bar to "kkkk" set Address to "kkkkkkkk" set Data_out_D3 to "1" set Write_enable_bar to "k" end vector !************************************************************************* !************************************************************************* sub Write_mode (In_Address, Data) execute Block_select_true execute Data execute In_Address execute Write_true execute Write_false execute Block_select_false end sub sub Read_mode (Out_Address, Data) execute Block_Select_true execute Out_Address execute Data execute Block_Select_false end sub sub Block_select_untrue execute Block_Select_false execute In_Address_00000000 execute Data_out_0000 end sub !AT The following subroutines have been added for a minimum pins test. !AT Vectors in the subroutine "Write_mode" reference the entire data bus. !AT Therefore this subroutine was copied and modified to reference only !AT a single pin of the data bus. The subroutine "Read_mode" did not !AT require any modification as all references to the data bus are made !AT via a passed parameter (Data). This reference can be modified in the !AT call statement. sub Write_mode_Dx (In_Address, Data_in_Dx, W_true_Dx, W_false_Dx) execute Block_select_true execute Data_in_Dx execute In_Address execute W_true_Dx execute W_false_Dx execute Block_select_false end sub !************************************************************************* !AT The following AwareTest units have been added for minimum pins tests. Each !AT unit tests a separate data pin starting with D0. unit "awaretest D0 Test" execute Block_select_false call Write_mode_Dx (In_Address_0_D0,Data_in_D0_0, W_true_D0, W_false_D0) call Read_mode (Out_Address_00000000,Data_out_D0_0) call Write_mode_Dx (In_Address_0_D0,Data_in_D0_1, W_true_D0, W_false_D0) call Read_mode (Out_Address_00000000,Data_out_D0_1) end unit unit "awaretest D1 Test" execute Block_select_false call Write_mode_Dx (In_Address_0_D1,Data_in_D1_0, W_true_D1, W_false_D1) call Read_mode (Out_Address_00000000,Data_out_D1_0) call Write_mode_Dx (In_Address_0_D1,Data_in_D1_1, W_true_D1, W_false_D1) call Read_mode (Out_Address_00000000,Data_out_D1_1) end unit unit "awaretest D2 Test" execute Block_select_false call Write_mode_Dx (In_Address_0_D2,Data_in_D2_0, W_true_D2, W_false_D2) call Read_mode (Out_Address_00000000,Data_out_D2_0) call Write_mode_Dx (In_Address_0_D2,Data_in_D2_1, W_true_D2, W_false_D2) call Read_mode (Out_Address_00000000,Data_out_D2_1) end unit unit "awaretest D3 Test" execute Block_select_false call Write_mode_Dx (In_Address_0_D3,Data_in_D3_0, W_true_D3, W_false_D3) call Read_mode (Out_Address_00000000,Data_out_D3_0) call Write_mode_Dx (In_Address_0_D3,Data_in_D3_1, W_true_D3, W_false_D3) call Read_mode (Out_Address_00000000,Data_out_D3_1) end unit unit "Test ram cells" execute Block_select_false ! Write pattern to ram cells call Write_mode (In_Address_00000000,Data_in_0000) call Write_mode (In_Address_00000001,Data_in_0001) call Write_mode (In_Address_00000011,Data_in_0011) call Write_mode (In_Address_00000111,Data_in_0111) call Write_mode (In_Address_00001111,Data_in_1111) call Write_mode (In_Address_00011111,Data_in_1110) call Write_mode (In_Address_00111111,Data_in_1100) call Write_mode (In_Address_01111111,Data_in_1000) call Write_mode (In_Address_11111111,Data_in_1001) ! Read pattern from ram cells call Read_mode (Out_Address_00000000,Data_out_0000) call Read_mode (Out_Address_00000001,Data_out_0001) call Read_mode (Out_Address_00000011,Data_out_0011) call Read_mode (Out_Address_00000111,Data_out_0111) call Read_mode (Out_Address_00001111,Data_out_1111) call Read_mode (Out_Address_00011111,Data_out_1110) call Read_mode (Out_Address_00111111,Data_out_1100) call Read_mode (Out_Address_01111111,Data_out_1000) call Read_mode (Out_Address_11111111,Data_out_1001) end unit unit "Test Block select lines" call Write_mode (In_Address_00000000,Data_in_1111) call Read_mode (Out_Address_00000000,Data_out_1111) call Block_select_untrue call Read_mode (Out_Address_00000000,Data_out_1111) end unit ! End of test