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U4154A AXIe-based Logic Analyzer Module

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Product Description

The Keysight Technologies U4154A AXIe-based logic analyzer system combines reliable data capture with powerful analysis and validation tools to enable you to quickly and confidently validate and debug high-speed digital designs operating at speeds up to 4 Gb/s.

Figure 1A shows the small eyes associated with a DDR3 system operating at 1.4 V at 2133 Mb/s. The U4154A logic analyzer uses its unique eye scan capability to automatically place the sampling point in both time and voltage within the eye on each individual channel for optimal sampling

reliability.

Figure 1B shows the trigger setup to capture a burst of 8 data samples. The trigger sequencer operates up to 2.5 Gb/s, enabling accurate and precise triggering.

Figure 1C and Figure 1D show the state listing and waveform for these data captures.

The 12.5 GHz Timing Zoom with 256 K sample memory gives you simultaneous state and high-resolution timing measurements covering a time span of 20 μs, which corresponds to 43680 clock cycles at a 2133 MHz clock rate.

Available memory depth up to 200 M samples allows you to debug very complex

problems where the cause and symptoms may be separated by several seconds. The amount of memory can upgraded after purchase; see the Upgrades section of the Ordering Information on page 16.

No need to sacrifice sampling resolution to view more system activity. In timing mode, if your system has bursts of activity followed by times with little activity, you can use transitional timing along with the logic analyzer’s deep memory to capture seconds to minutes of activity at 400 ps sampling resolution at a sample frequency of 2.5 GHz. You also have the flexibility to increase the amount of time captured by excluding certain buses or signals from the transition detector. For example, you can exclude clock or strobe signals that add little useful information to the measurement. In State mode, select Store Qualification to save states of interest into memory.

The dual-sample mode for DDR memory signals up to 2.5 Gb/s allows for the separation of reads from writes with automatic setup of the correct sampling positions for each. This mode also allows acquisition of state (synchronous) data at rates up to 4 Gb/s. When used in this mode, the data will appear in two labels. One label for rising edge and another for falling edge captures. The logic analyzer will be clocked with one edge of the system clock. Labels can be merged using the Keysight B4602A Signal Extractor tool. When operated in dual-sample mode on all pods, the channel count is 68 channels for one U4154A, or 136 channels for two U4154As combined. Dual-sample mode can be selected on a per-pod-pair basis, so if you have only a subset of signals that require dual-sample mode, the channel count can be higher.

A burst-mode clock allows you to take measurements that include periods of inactivity on the clock, such as power management transitions when the clock is inactive.

Make faster, easier, more powerful DDR measurements

The DDR setup assistant simplifies measurement setup and minimizes the time to make your first measurement. The DDR setup tool guides you through even the most complex DDR setup in minutes. DDR eye scan makes it easy to determine the optimum acquisition sample point without requiring an oscilloscope. Keysight qualified scans place the sample position at the center of the eye on every individual channel for maximum data capture reliability, including separate sampling positions for read and write data.

The DDR setup assistant includes a variety of powerful, time-saving trigger features optimized for DDR measurements. Burst trigger captures an entire data burst of 8 data samples on DDR2/3 systems from one sequence level in the trigger menu. Intuitive trigger macros with diagrams provide visualization of triggering options and simplify the process of creating triggers.

As timing and voltage margins continue to shrink, confidence in signal integrity becomes an increasingly vital requirement in the design validation process. Eye scan lets you acquire signal integrity information on all the buses in your design, under a wide variety of operating conditions, in a matter of minutes. Identify problem signals quickly for further investigation with an oscilloscope. Results can be viewed for each individual signal or as a composite of multiple signals or buses. Support up to 4 clock qualifiers, isolate scans of any signal from any combination of other signals, use full-triggering capabilities for scan qualification, and analyze specific system activity with customizable viewing windows to sample only when the qualifying signal is active. The eye scan technology in the U4154A provides insights that can’t be achieved with any other test method.

DDR eye scan automatically groups signals so you can quickly spot byte lane-related signal integrity problems. Scans can be qualified based on trigger-state criteria, thus providing unique insight. For example, read and write scans can be separated for greater insight. Burst scan allows you to gather signal integrity information on two read or write cycles separated by only one cycle.

Improve Signal Integrity with Eye Scan Technology

As timing and voltage margins continue to shrink, confidence in signal integrity becomes an increasingly vital requirement in the design validation process. Eye scan lets you acquire signal integrity information on all the buses in your design, under a wide variety of operating conditions, in a matter of minutes. Identify problem signals quickly for further investigation with an oscilloscope. Results can be viewed for each individual signal or as a composite of multiple signals or buses. Support up to 4 clock qualifiers, isolate scans of any signal from any combination of other signals, use full-triggering capabilities for scan qualification, and analyze specific system activity with customizable viewing windows to sample only when the qualifying signal is active. The eye scan technology in the U4154A provides insights that can’t be achieved with any other test method.

DDR eye scan automatically groups signals so you can quickly spot byte lane-related signal integrity problems. Scans can be qualified based on trigger-state criteria, thus providing unique insight. For example, read and write scans can be separated for greater insight. Burst scan allows you to gather signal integrity information on two read or write cycles separated by only one cycle.

Harness your logic analyzer and scope for powerful insight

Combine the powerful triggering and protocol analysis of a logic analyzer with the signal

integrity insight of to solve tough design problems. Keysight ViewScope allows you to an oscilloscope easily make time-correlated measurements between Keysight logic analyzers and oscilloscopes. The time-correlated logic analyzer and oscilloscope waveforms are integrated into a single logic analyzer waveform display for easy viewing and analysis. You can also trigger the oscilloscope from the logic analyzer (or vice versa), and automatically de-skew the two instruments.

ViewScope enables you to perform the following tasks more easily, quickly, and effectively:

•Validate signal integrity

•Track down problems caused by signal integrity

•Determine correct operation of A/D and D/A converters

•Access correct logical and timing relationships between the analog and digital portions of a design

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