Column Control DTX

J-BERT N4903B High-Performance Serial BERT

Data Sheets

Keysight offers a wide range of serial bit error ratio test (BERT) solutions for R&D and manufacturing. The J-BERT N4903B high-performance serial BERT is the flagship of Keysight’s N4900 serial BERT series. It addresses the needs of R&D and validation teams who characterize serial I/O ports or ASICs up to 14.2 Gb/s. The data rate can be extended up to 28.4 Gb/s by adding a 2:1 multiplexer and demultiplexer with clock data recovery. Integrated and calibrated jitter sources for jitter tolerance measurements allow designers to characterize and prove compliance of their receiver’s jitter tolerance.

Keysight’s N4900 serial BERT series offers key benefits:

  • Excellent precision and sensitivity for accurate measurements
  • Choice of feature set and frequency classes to tailor to test needs and budget
  • State-of-the-art user interfaces with color touch screen
  • Remote control via LAN, USB and GPIB interfaces, compatible with existing command set Keysight 71612, 81630A Series, N4900 Series
  • Small form factor saves rack or bench space

Serial BERTs for R&D and validation labs


The J-BERT M8020A is the new generation high-performance BERT that enables fast and accurate receiver characterization of single- and multi-lane devices operating up to 16 or 32 Gb/s.


The J-BERT N4903B high-performance serial BERT is the ideal choice for characterization. It offers calibrated jitter tolerance tests fully integrated in a high-performance BERT.


The N4960A 17 and 32Gb/s Serial BERT is an affordable and compact Serial BERT. It is the perfect solution to test multiple channels for 100 Gigabit Ethernet applications.


The N4967A Serial BERT System allows characterization of optical transceivers operating up to 44 Gb/s.

Serial BERTs for manufacturing test of optical transceivers


The N5980A manufacturing serial BERT up to 3.125 Gb/s data rate enables transceiver test at up to one-sixth of the test cost and the front panel size of comparable BERT solutions.


The N2101B PXIT manufacturing BERT is a PXI module that has been designed for testing optical transceivers up to 10.3125 Gb/s.


The N4906B serial BERT offers an economic BERT solution with excellent signal performance up to 12.5 Gb/s for manufacturing and telecom device testing.

J-BERT N4903B High-Performance Serial BERT

The J-BERT N4903B high-performance serial BERT provides the most complete jitter tolerance test for embedded and forwarded clock devices.

It is the ideal choice for R&D and validation teams characterizing and stressing chips and transceiver modules that have serial I/O ports up to 7 Gb/s, 12.5 Gb/s or even 14.2 Gb/s. It can

characterize a receiver’s jitter tolerance and is designed to prove compliance to today’s most popular serial bus standards, such as:

PCI Express

  • DisplayPort
  • USB Super Speed
  • Thunderbolt
  • Fibre Channel
  • QPI
  • Memory buses, such as fully buffered DIMM2
  • Backplanes, such as CEI, IEEE, Infiniband
  • 10 GbE/ XAUI
  • 100 GbE (10x 10G or 4x 25G)

Accurate characterization is achieved with clean signals from the pattern generator, which features exceptionally low jitter and extremely fast transition times. Built-in and calibrated jitter sources allow accurate jitter tolerance testing of receivers.

Test set-up is simplified significantly, because the J-BERT N4903B is designed to match serial bus standards optimally. It offers: differential I/Os, variable voltage levels on all signal outputs, built-in jitter and ISI, pattern sequencer, reference clock outputs, tunable CDR, pattern capture and bit recovery mode to analyze clock-less and non-deterministic patterns.

Faster test execution is possible with J-BERT’s automated jitter tolerance tests and fast total jitter measurements.

J-BERT N4903B The Most Complete Jitter Tolerance Test Solution

The J-BERT N4903B is a long-term investment which is configurable for today’s test and budget requirements but also allows upgrades from the N4903A model, and later retrofit of all options and full speed when test needs change.

To expand the use of J-BERT a 4-tap de-emphasis, a reference clock multiplier, a 28 Gb/s 2:1 multiplexer, and a 32 Gb/s CDR with de-multiplexer can be added to the setup.

J-BERT N4903B The Most Complete Jitter Tolerance Test Solution (continued)

Key capabilities of J-BERT N4903B

  • Data rate range from 150 to 7 or 12.5 or 14.2 Gb/s
  • Calibrated and built-in jitter and interference sources ( SJ, PJ1, PJ2, SSC, residual SSC, arbitrary SSC, RJ, BUJ, cm/dm SI, switchable ISI traces) plus external delay modulation input.
  • Supports all clock topologies: embedded clock, forwarded clock and reference clocked
  • Second output channel with independent pattern + PRBS
  • Excellent signal performance and sensitivity
  • Pattern sequencer with 120 blocks, 32Mbit memory and PRBS
  • Electrical idle
  • Built-in tunable CDR always included
  • Error analysis of 8b/10b and 128b/130b coded and packetized data. Filtering of definable filler symbols or PCIe® SKPOS
  • Extension to data rates up to 28.4Gb/s possible
  • Extension with 4-tap de-emphasis possible
  • Available as pattern generator version
  • Upgrade path from N4903A


Please have a salesperson contact me.

*Indicates required field

Select a preferred method of communication*Required Field
Preferred method of communication? Change email?
Preferred method of communication?

By continuing, you are providing Keysight with your personal data. See the Keysight Privacy Statement for information on how we use this data.

Thank you

A sales representative will contact you soon.

Column Control DTX