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Predicting Ka-band Transceiver Thermal Margins, Wear, and Lifespan

Case Studies


• EnSilica



• Predicting RF chip reliability in harsh automotive settings with more confidence than estimates provide

• Design cycles slowed by time-consuming physical lab thermal test setups

• Integrate electro-thermal simulation into existing RF EDA workflow



• Shift thermal analysis into virtual space with minimal extra steps by adding PathWave ADS  Electro-Thermal Simulator, extending electromagnetic simulation capability

• Enhance thermal models with chip packaging info, PCB layout and materials, and more



• Less than 0.7°C difference between thermal simulation and measurements

• Chip layout and bumping changes improved thermal margins

• High-confidence 10-yr reliability prediction


Thermal Analysis Crucial for “First-Time Right”


EnSilica, Ltd., based in Abingdon, UK, is a fabless chipmaker creating custom ASICs for OEMs and system integrators and providing IC design services for companies with in-house design teams. EnSilica’s world-class expertise in RF, mmWave, mixed-signal, and high-speed digital designs helps customers in automotive, communications, industrial, healthcare, and wearable applications.


“First-time right” is EnSilica’s demanding standard for chips when frequencies and complexity rise. EnSilica has an RF/analog team of about 25 engineers based in the UK and about 130 engineers in total across offices worldwide. Their RF experience includes designs up to 40 GHz and foundry relationships for reliable processes. Domain-specific knowledge and accelerated time to market achieved through design reuse are two more reasons customers turn to EnSilica.


One use case for EnSilica’s Ka-band (26.5-40 GHz) transceivers is vehicle-mounted low-earth orbit (LEO) satellite terminals, where harsh temperatures can wear parts out faster than expected. Assessing the thermal performance of these transceivers using Keysight PathWave Advanced Design System (ADS), PathWave RFPro, and PathWave ADS Electro-Thermal Simulator is vital in understanding their thermal operating margin and lifespan. Simulations reduce time-consuming physical test setups and provide accurate, comprehensive electro-magnetic and electro-thermal analysis with fully coupled effects, in turn enabling reliability predictions with higher confidence.


Challenge: Predicting how long chips can withstand wear


Automotive environments are notorious for being one of the harshest on earth, with broad temperature ranges designers must take into account. Temperatures can span from freezing to boiling when vehicles sit outside. Engine compartments generate concentrated heat, exposing components to even higher temperatures. Sun loading can heat surfaces and passenger compartments to uncomfortable levels. Electronics also self-heat – higher frequencies and transmit power levels drive up readings.


Heat kills semiconductors. CMOS transistors follow a classical “bathtub” curve of failure rates. Some failures occur immediately, termed infant mortality; operational burn-in screening can weed these out effectively. Robust board-level thermal design practices, like proper component spacing, spreading planes, thermal vias, heatsinking, and airflow management can contain many hotspots.


The ultimate killer is wear-out failures, setting a practical limit to the functional life of a device. CMOS transistors age due to hot carrier injection, bias temperature instability, and electron migration. Voltage and junction temperature variations impact these effects. To better predict wear-out, foundries often provide “aged” transistor models in their automotive-qualified processes, which gives a starting point. 


In complex designs, context matters. “Knowing where the edge of our chip is and caring about how customers use it is important,” says Alan Wong, Sr. VP of Engineering at EnSilica. “Customers come to us because we have a deeper understanding of system applications and how to make a chip that behaves as expected in a system.” A big part of that understanding comes from thermal analysis.


Traditionally, system vendors have performed cursory thermal simulations, then moved into physical prototypes to test and measure real-world thermal behavior in a lab. Testing can include various accelerated life cycle test (ALT) techniques. If designs underperform expectations, adjustments can be expensive – including changing board layouts, forcing the selection of different chips, or limiting operating specifications, leading to missed market windows and lost sales.


To help its customers, EnSilica decided to take on more thermal characterization of its parts. But it would not be easy. “We were relying on hand calculations using physical design rules and estimates of electron migration,” observes Wong. “Third-party packaging suppliers would help by telling us how hot a die might get when packaged based on their thermal dissipation experience, but it was just an educated guess, and it wasn’t detailed enough to guide design decisions.”


Looking for better thermal data, EnSilica began instrumenting its chip designs. Low-power temperature sensors embedded at points on a die give temperature readings. Two issues soon arise. Are the sensors placed in the right spots? And is the chip in the proper operating mode for taking valid measurements? Experience helps with sensor placement but setting up even a limited number of test conditions and sweeping the environmental chamber’s temperature takes time.


Predictions from thermal estimates lacked certainty and physical test and measurement setups for improved thermal characterization were slowing development by weeks.


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