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This application note shows how power integrity (PI) engineers can select decoupling capacitor values to avoid resonant impedance peaks in the power delivery. Simply leveraging capacitor values from past designs or data sheet examples is risky when design margins keep diminishing with lower power rail voltages, higher currents, and faster data rates. Modern simulation tools can provide a complete Power Integrity workflow to optimize the PI ecosystem and avoid failures like EMI/EMC late in the design cycle.