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DesignCon
Visit Us in Booth 807
High-speed digital standards are quickly evolving to keep pace with emerging technologies. Each generational change introduces new test challenges for your digital designs to innovate next. You need to test your high-speed digital designs across all product development stages — from design and simulation, analysis, debug, and compliance test. We can help you anticipate test challenges, optimize performance, and accelerate time-to-market of your high-speed computing interfaces, data center connections, and consumer electronics.
Join Keysight, DesignCon 2021 Host Sponsor, at our Booth 807 to discuss how we can help you anticipate test challenges, optimize performance, and accelerate your time-to-market. On Tuesday, August 17th, visit the Chiphead Theatre from 2:15 to 2:55 p.m. for the Modernization of Test and Measurement technical session.
DATE
August 16 – 18, 2021
LOCATION
San Jose McEnery Convention Center
150 West San Carlos Street
San Jose, CA 95113
BOOTH 807
Program Details
Keysight’s technical experts and application engineers will demonstrate the most advanced design and test solutions, developed for solving today’s most difficult high-speed digital measurement challenges.
Keysight is proud to be the host sponsor of DesignCon 2021.
KEYSIGHT EDUCATION FORUM (KEF)
Exec Ballroom 210E
We are pleased to offer you all 8 Keysight Education Forum (KEF) sessions free of charge. Keysight’s test and measurement experts continue with KEF 2021 to showcase undeniable leadership and commitment across the high-speed digital and semiconductor markets.
Tuesday, August 17th Sessions
8:30 a.m. – 9:10 a.m.
Advanced Testing Challenges at 32GBaud PAM4 with PCIe 6.0
9:20 a.m. – 10:05 a.m.
Next Gen Development in Type-C Ecosystem
11:15 a.m. – 11:45 a.m.
Physical Layer Validation Challenges of Characterizing 100 Gbps/lane Designs
12:05 a.m. – 12:45 p.m.
Solving Your Forward Error Correction Problems
Wednesday, August 18th Sessions
8:30 a.m. – 9:10 a.m.
Guide to Recalibrate Your Signal Integrity Intuition for Memory Interfaces
9:20 a.m. – 10:05 a.m.
Ramping up on the Latest Skills for Power Integrity Design/Debug
11:15 a.m. – 11:45 a.m.
Next-Generation Memory Solutions
12:05 a.m. – 12:45 p.m.
Explore Why Testing Disaggregated 5G Elements in Isolations is Required to Ensure Proper O-RAN Fronthaul Conformance
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