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Keysight empowers innovators to break data speed records as they connect and secure the world. Whether you are pursuing 800G or 1.6T data speeds to accelerate the development of intelligent networks for artificial intelligence (AI) workloads, we empower you. Optimize your electrical and optical transmissions and data center interconnects with our leading design, emulation, and test solutions.
DATE
January 29 – 30, 2025
LOCATION
Santa Clara Convention Center
Santa Clara, California
KEYSIGHT BOOTH
1039
Discover Application Demonstrations
Visit us at Booth 1039, January 29 to 30, to see demos in action
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Keysight EDA and ADS
Keysight Chiplet PHY Designer is an advanced design tool that analyzes and optimizes chiplet-based systems, focusing on the UCIe and Bunch of Wires (BoW) standards. This cutting-edge tool empowers designers to gain in-depth insights into their designs, identify potential bottlenecks, and implement optimizations that enhance system integration and overall performance in chiplet-based architectures.
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PCIe® PAM4 Test Solutions
Keysight PCIe® test solutions cover design and protocol testing. Demo highlights include the P557xA protocol analyzer and exerciser products and physical layer test tools such as the UXR-Series oscilloscope and M8050A bit error rate testing (BERT) platform.
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Validation of 1.6 Tbps PHY
Using the Keysight UXR-Series oscilloscope and D90203DJC electrical transmitter compliance test software, we will demonstrate how to efficiently test P802.3dj Ethernet (1.6 Tbps).
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448 Gbps Research
The next-generation interconnect architecture for high-performance artificial intelligence (AI) clusters is advancing to 448 Gbps interfaces for 3.2Tbps systems sooner than expected. Keysight will showcase its M8199B arbitrary waveform generator and other key tools enabling this technology.
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1.6 Tbps Signal Integrity
Physical Layer Test System (PLTS) 2025 is advanced signal integrity application software that streamlines the calibration, measurement, and post-processing of vector network analyzer and time domain reflectometer data. It accelerates time to market for high-speed digital interconnects such as backplanes, printed circuit boards, cables, and connectors — critical internet infrastructure components that demand high-bandwidth design.
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AI at the Edge
Keysight will showcase comprehensive USB4 solutions for compliance and validation using the UXR-Series oscilloscope and the M8040A / M8050A BERT platform.
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800G AI Interconnect
The Keysight Interconnect and Network Performance Tester 800GE, the benchtop PAM4 Ethernet test system, and the AI Data Center Test Builder measure optical and electrical interconnect BER and perform forward error correction — essential for high-data-volume AI applications.
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Next-Generation Memory Validation
Next-generation memory designs require lower noise and reduced loading to reflect design performance accurately. This demo showcases the Keysight D9060LDDC LPDDR6 test application to validate the capabilities of next-generation LPDDR6 memory designs.
Keysight Education Forum
Ballroom K
Wednesday, January 29, Sessions
The Road to PCIe® 7.0: Advanced Testing Challenges at 32 Gbaud PAM4
8:00 to 8:45 a.m.
IEEE 802.3dj 212G Physical Validation
8:55 to 9:40 a.m.
DesignCon Keynote
10:00 to 11:00 a.m.
UCIe vs. BoW: Choosing the Right Chiplet Standard
11:00 to 11:40 a.m.
LPDDR5X SI / PI Simulation and Evaluation Challenges
11:50 a.m. to 12:30 p.m.
OIF-CEI 112G Linear Pluggable Optics Validation
12:40 to 1:20 p.m.
Navigating the Challenges Testing USB 80 Gbps
1:30 to 2:10 p.m.
LPDDR5 System Level SI / PI Simulation for the Edge Artificial Intelligence System
2:20 to 3:00 p.m.
Systematic and Accurate Cross-Talk Analysis
3:10 to 3:50 p.m.
Design Data and IP Management
4:00 to 4:40 p.m.
Benchmarking Collective Operations: A Key to Optimizing AI Infrastructure Performance
4:50 to 5:30 p.m.
Conference Papers by Keysight
Date |
Start time |
Session title |
Session type |
Room |
|---|---|---|---|---|
| January 28 | 9:00 a.m. |
Tutorial — Channel De-Embedding Methodology for Rx Stress Testing Using Fast-Edge Tx Waveform of BERT |
Tutorial |
Ballroom B |
| January 28 | 9:00 a.m. |
Tutorial — Power Delivery Network Master Class on 2000A: How to Design, Simulate, and Validate |
Tutorial |
Ballroom A |
| January 28 | 2:00 p.m. |
Tutorial — COM: A Field Guide for Serial Communication Link Designers |
Tutorial |
Ballroom D |
| January 28 | 4:45 p.m. |
Panel — PCI Express and PAM4: Balancing Silicon and Interconnect Interdependencies for 128 GT/s |
Technical Panel |
Ballroom B |
| January 29 | 8:00 a.m. | Practical Implementation of Insertion Loss Correction and Delay Characterization of Test Fixtures Used for 200 Gb/s Per Lane Conformance Testing | Technical Paper Session | Ballroom E |
| January 29 | 11:15 a.m. | Solving Common Problems with PCB Power Integrity Measurements and Simulations | Chiphead Theater Session | Chiphead Theater |
| January 29 | 12:15 p.m. |
IBIS-AMI Modeling and Simulation of DMT in Preparation for 448 Gbps Applications |
Technical Paper Session |
Ballroom F |
| January 29 | 2:00 p.m. |
Transmitter Power Spectral Density Noise Impact for 200 Gb/s PAM4 per Lane |
Technical Paper Session |
Ballroom C |
| January 29 | 4:00 p.m | Panel — Test on Wheels: Test and Measurement for Automotive Standards | Technical Paper | Ballroom H |
| January 30 | 9:00 a.m. | Innovative Design of 224G BGA Pin Map and Via Structure | Technical Paper Session | Ballroom D |
| January 30 | 9:00 a.m. | IBIS-AMI Modeling Formulation for Bidirectional MultiGBase-T1 Automotive Ethernet Links | Technical Paper Session | Ballroom C |
| January 30 | 11:15 a.m. | Modeling and Parameter Extraction of 224G PCB Under Variable Temperature and Research on the Influence of Temperature on Signal Integrity | Technical Paper Session | Ballroom B |
| January 30 | 12:15 p.m. | Beyond 200G: Brick Walls of 400G links per Lane | Technical Paper Session | Ballroom G |
| January 30 | 2:00 p.m | Accurate Adapter Removal in High-Precision, Low-Loss RF Interconnect Characterization | Technical Paper Session | Ballroom G |
| January 30 | 3:00 p.m. | It Takes a Village: 224Gb/s Mated Test Fixtures for Compliance | Technical Paper Session | Ballroom F |
| January 30 | 4:00 p.m. | Panel — Unbaking the Cake: The New Science of Compensating for Instrument Noise in Serial Data Measurements | Technical Paper Session | Ballroom C |
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