Column Control DTX

Power Integrity for 32 Gb/s SERDES Transceivers

White Papers

Power integrity is about getting the right power to the load. At 32 Gb/s the challenges of designing a low noise power delivery network are not just the fast edge speeds and diminishing timing margins. The lower signaling voltages also provide a problem. Leveraging past designs to sprinkle decoupling capacitors across modern applications with numerous low voltage dc-dc converters can create unexpected noise sources and extra part counts. A 32 Gb/s FPGA will be used to show how transmitter jitter is improved by engineering the impedance of the PDN ecosystem and at the same time reducing the part count.

×

Please have a salesperson contact me.

*Indicates required field

Preferred method of communication? *Required Field
Preferred method of communication? Change email?
Preferred method of communication?

By clicking the button, you are providing Keysight with your personal data. See the Keysight Privacy Statement for information on how we use this data.

Thank you.

A sales representative will contact you soon.

Column Control DTX