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SEPTEMBER 24, 2020 (all times are Central European Summer Time)

 10:00 a.m. – Keynote: Scaling HPC SoC Designs in the Era of AI with Silicon IP
Learn the silicon IP market trends in high-performance computing System-on-chip designs and how to achieve your latency, power, and bandwidth goals.

10:30 a.m. – Prepare to Test and Avoid Pitfalls in USB4 Implementations
Prepare to test next-gen USB Type-C® technologies with the right test methodologies.

11:00 a.m. – Data Center Technologies Move Toward $1/Gigabit
Understand how next-generation data center technologies help the industry to drastically reduce the cost of data center interconnects.

11:30 a.m. – Demo Break

11:45 a.m. – On-Wafer / Die Test for Photonic Integrated Circuits
Effective and fast optical and electro-optical wafer- and die-level testing with surface and edge coupling.

12:15 p.m. – Improve Device Performance Using Power Integrity Test Tools
Understand common Power Integrity and PMIC design issues. Improve test accuracy and efficiency by adopting the latest Power Integrity techniques.

12:45 p.m. – Demo Break

1:00 p.m. – Test & Measurement Tradeoffs for 400G Transmitter Designs
Understand the difference between leveraging Real time scopes and/or Equivalent time sampling scopes platforms & when to use each for Ultra high speed digital designs.

1:30 p.m. – Enhancing Data Throughput - Every. Little. Thing. Matters.
Equalization, de-embedding and forward error correction all allow design engineers to push more data through a limited channel. This paper walks through the various techniques to make understanding them simple.

2:00 p.m. – Data Center and Optical Network Ecosystem to Enable 5G
Deep dive with Thought leaders and experts from industry & discuss wireline innovations in this session.