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E4829B Parallel Cell/Traffic Generator and Analyzer System

Статус продукта: Устарело | Варианты сервисной поддержки
Этот продукт больше не поставляется

Для данного продукта вариантов замены не найдено.

Ключевые возможности и технические характеристики

  • Flexible cell structure and size from 16 to 128 word cell length
  • Exercise ATM switch fabric by stimulating and analyzing cells with routing tag added to the standard ATM cell structure
  • Flexible traffic shaping
  • Verify policing functions of ATM fabric
  • Stress physical devices for proper operation at corner cases
  • Real-time HEC, CRC-10, time stamping generation and analysis
  • Measures cell error ratio, cell transit delay, cell transit variation, cell loss, header translation
  • Connects to 8/16 bit custom or UTOPIA level 1 and 2 interfaces

Описание

The Keysight E4829B parallel cell/traffic generator and analyzer system is a comprehensive verification and debugging tool for today's cell based communication designs like ATM chips, ASICs, hubs, switches, and cross-connects. Connecting to parallel interfaces like the 8/16 bit wide UTOPIA level 1 and 2 or similar proprietary interfaces, the system meets the requirements for design verification of chips, ASICs and sub modules, as well as speeding up board/system debugging and root cause analysis.

The concept of building cells out of single real-time generated and memory-based data segments allows you to handle standard ATM cells as well as proprietary ones, e.g., ATM cells with additional routing tags. Four independent traffic generators support single, periodic, and random cell burst. Full deterministic cell traffic can be set up. The cell trigger capabilities allow the user to detect dedicated cells, cell patterns, CRC-10, and HEC errors at real time as an event. Single or multiple events can be combined to start cell acquisition, event count or real-time processing like time stamp analysis for statistical measurements.

For complete details, click on the Technical Data Sheet / Product Overview link.

  • Flexible cell structure and size from 16 to 128 word cell length
  • Exercise ATM switch fabric by stimulating and analyzing cells with routing tag added to the standard ATM cell structure
  • Flexible traffic shaping
  • Verify policing functions of ATM fabric
  • Stress physical devices for proper operation at corner cases
  • Real-time HEC, CRC-10, time stamping generation and analysis
  • Measures cell error ratio, cell transit delay, cell transit variation, cell loss, header translation
  • Connects to 8/16 bit custom or UTOPIA level 1 and 2 interfaces