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Preço para o: Brasil

* Os preços não incluem impostos ou taxas, os quais deverão ser considerados na oportunidade em que emitida a cotação formal, conforme determinação das autoridades governamentais competentes. Os preços mostrados são os preços de varejo sugeridos pelo fabricante (MSRP). Os preços apresentados não incluem impostos.

Principais recursos e especificações

The Advanced Design System (ADS) Advanced Layout Element:

  • Layout Versus Schematic (LVS)
    - Device recognition LVS
    - LVS with Physical Nets
    - Module-level LVS
  • Manufacturing Grid
  • Silicon dummy metal fill utility
  • Layout net names from Schematic

Descrição

Advanced Design System (ADS)The W2320EP Advanced Layout Element provides access to additional ADS layout capabilities for Layout verification and manufacturing output, Silicon RFIC utilities, and Multi-technology enhancements.

  • Device recognition LVS: The industry-standard methodology for IC verification. It’s based on the physical properties of the layout and closely models the manufacturing process. Requires a rules file.
  • LVS with Physical Nets: Traces and verifies physical connections between component.
  • Module-level LVS: Component Based LVS on Module Designs with Bond wires & Nested Technology. Finds module-level wiring and pin swap errors. ICs can contain fixed layout artwork or nested technology.
  • Manufacturing Grid: identifies layout objects which are off grid, quickly align off grid objects to the manufacturing grid, manual off-grid override.
  • Silicon dummy metal fill utility: provides the designer and layout engineer an easy to use tool to generate dummy metal fills for silicon RFICs. Target required metal density and validate metal fill effects on the design with Momentum early in the design process.
  • Layout net names from Schematic: quickly and easily update layout netname with net name from the schematic.