!-----------------------------------------------------------------------
!  Copyright (c) Hewlett-Packard Company 1997
!
!  All Rights Reserved.  Reproduction, adaptation, or translation
!  without prior written permission is prohibited, except as allowed
!  under the copyright laws.
!
!-----------------------------------------------------------------------
!
! Device        : uPD488170L
! Manufacturer  : NEC
! Description   : 18M-BIT RAMBUS DRAM
! Package       : 72/36-pin PSSOP
! Test Platform : HP3070
! Safeguard     : high_out_cmos
!-----------------------------------------------------------------------
!
! Chip Marking:
!               NEC  JAPAN
!               D488170LG6-A50
!               9643L9004
!
! There are 15 active pins in the test.
! 10   are partially tested.      ( 66.67 %)
! 5    are not tested.            ( 33.33 %)
!
!
!  Pin     Drive  Fault(s)  Receive Fault(s)
! -----    ---------------  ----------------
! 3        SA-0 SA-1 SA-X   SA-1 SA-X
! 5        SA-0 SA-1 SA-X   SA-1 SA-X
! 7        SA-1 SA-X
! 9        SA-0 SA-1 SA-X   SA-1 SA-X
! 11       SA-0 SA-1 SA-X   SA-1 SA-X
! 13       SA-0 SA-1 SA-X
! 15       SA-0 SA-1 SA-X
! 17       SA-0 SA-1 SA-X   SA-1 SA-X
! 19       SA-0 SA-1 SA-X   SA-0 SA-1 SA-X
! 20       SA-0 SA-1 SA-X
! 22                        SA-0 SA-1 SA-X
! 23       SA-0 SA-1 SA-X   SA-1 SA-X
! 25       SA-0 SA-1 SA-X   SA-1 SA-X
! 27       SA-0 SA-1 SA-X   SA-1 SA-X
! 29       SA-0 SA-1 SA-X   SA-1 SA-X
!------------------------------------------------------------------------------

sequential
vector  cycle 500n
receive delay 400n

!------------------------------------------------------------------------------
!                     ASSIGNMENT SECTION
!------------------------------------------------------------------------------
assign   VCC            to pins   1,  8, 12, 16, 32

assign   GND            to pins   2,  4, 10, 14, 18, 24, 28, 31

assign   RXCLK_I        to pins  13
assign   TXCLK_I        to pins  15
assign   BUSENABLE_I    to pins   7
assign   SIN_I          to pins  20

assign   SOUT_O         to pins  22

assign   BUSDATA_8_0_B  to pins   3,  5,  9, 11, 17, 23, 25, 27, 29
assign   BUSCTRL_B      to pins  19

assign   NC_N           to pins   6, 21, 26, 30

assign   Disable_pins   to pins   7, 15, 13

family   TTL
format hexadecimal   BUSDATA_8_0_B
power    VCC, GND

inputs   RXCLK_I, TXCLK_I, BUSENABLE_I
inputs   SIN_I

outputs  SOUT_O

bidirectional  BUSDATA_8_0_B, BUSCTRL_B

nondigital     NC_N

disable  BUSDATA_8_0_B     with Disable_pins to "0tt" 100 times
disable  BUSCTRL_B         with Disable_pins to "0tt" 100 times

set load on groups BUSDATA_8_0_B to pull up

warning  "This is a P&PO test only.  Pins are tested for orientation."
!------------------------------------------------------------------------------
!                   VECTOR SECTION
!------------------------------------------------------------------------------

vector  Initialize_Inputs
   drive BUSDATA_8_0_B
   drive BUSCTRL_B
   set   BUSDATA_8_0_B  to "1FF"
   set   BUSCTRL_B      to "1"
   set   RXCLK_I        to "1"
   set   TXCLK_I        to "1"
   set   BUSENABLE_I    to "1"
   set   SIN_I          to "1"
end vector

vector  Keep
   drive BUSDATA_8_0_B
!        receive BUSCTRL_B
   drive BUSCTRL_B
   set   BUSDATA_8_0_B  to "kkk"
   set   BUSCTRL_B      to "k"
   set   RXCLK_I        to "k"
   set   TXCLK_I        to "k"
   set   BUSENABLE_I    to "k"
   set   SIN_I          to "k"
end vector

vector  RXCLK_I_hi
   initialize           to Keep
   set   RXCLK_I        to "1"
end vector

vector  RXCLK_I_lo
   initialize           to Keep
   set   RXCLK_I        to "0"
end vector

vector  R_Clock
   initialize           to Keep
   set   RXCLK_I        to "t"
end vector

vector  TXCLK_I_hi
   initialize           to Keep
   set   TXCLK_I        to "1"
end vector

vector  TXCLK_I_lo
   initialize           to Keep
   set   TXCLK_I        to "0"
end vector

vector  T_Clock
   initialize           to Keep
   set   TXCLK_I        to "t"
end vector

vector  BUSENABLE_I_hi
   initialize           to Keep
   set   BUSENABLE_I    to "1"
end vector

vector  BUSENABLE_I_lo
   initialize           to Keep
   set   BUSENABLE_I    to "0"
end vector

vector  SIN_I_hi
   initialize           to Keep
   set   SIN_I          to "1"
end vector

vector  SIN_I_lo
   initialize           to Keep
   set   SIN_I          to "0"
end vector

vector  SOUT_O_hi
   initialize           to Keep
   set   SOUT_O         to "1"
end vector

vector  SOUT_O_lo
   initialize           to Keep
   set   SOUT_O         to "0"
end vector

vector  BUSDATA_8_0_B_XXX_D
   initialize           to Keep
   drive BUSDATA_8_0_B
   set   BUSDATA_8_0_B  to "XXX"
end vector

vector  BUSCTRL_B_hi_D
   initialize           to Keep
   drive BUSCTRL_B
   set   BUSCTRL_B      to "1"
end vector

vector  BUSCTRL_B_lo_D
   initialize           to Keep
   drive BUSCTRL_B
   set   BUSCTRL_B      to "0"
end vector

vector  BUSCTRL_B_hi_R
   initialize           to Keep
   receive  BUSCTRL_B
   set   BUSCTRL_B      to "1"
end vector

vector  BUSCTRL_B_lo_R
   initialize           to Keep
   receive  BUSCTRL_B
   set   BUSCTRL_B      to "0"
end vector

vector  BUSDATA_8_0_B_XXC_R
   initialize           to Keep
   format binary        BUSDATA_8_0_B
   receive  BUSDATA_8_0_B
   set   BUSDATA_8_0_B  to "XXXXX11XX"
   format hexadecimal   BUSDATA_8_0_B
end vector

vector  BUSDATA_8_0_B_1FF_R
   initialize           to Keep
   receive  BUSDATA_8_0_B
   set   BUSDATA_8_0_B  to "1FF"
end vector

!------------------------------------------------------------------------------
!             UNIT SECTION
!------------------------------------------------------------------------------
unit  " Test1 : RESET and Clocking...."
   execute  Initialize_Inputs
   execute  BUSENABLE_I_Hi
   repeat   300 times
      execute  T_Clock
      execute  BUSDATA_8_0_B_1FF_R
   end repeat
end unit
!------------------------------------------------------------------------------

! End of TEST.