!!!!    6    0    1  987179758  Vcc7b                                         

! Device           : 7130
! Function         : CMOS Dual-port Ram 8K
! revision         : B.01.00
! safeguard        : high_out_cmos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

!Integrated Device Technology, Inc. data sheet

!safeguard is "high_out_cmos"

sequential

assign VCC                    to pins 48
assign GND                    to pins 24

assign CE_bar_left            to pins 1
assign RW_bar_left            to pins 2
assign OE_bar_left            to pins 5
assign Add_left               to pins 15,14,13,12,11
assign Add_left               to pins 10,9,8,7,6

assign BUSY_bar_left          to pins 3
assign INT_bar_left           to pins 4

assign IO_port_left           to pins 23,22,21,20
assign IO_port_left           to pins 19,18,17,16
assign IO_port_left_D0        to pins 16   !AT Added for minimum pin test.
assign IO_port_left_D1        to pins 17   !AT Added for minimum pin test.
assign IO_port_left_D2        to pins 18   !AT Added for minimum pin test.
assign IO_port_left_D3        to pins 19   !AT Added for minimum pin test.
assign IO_port_left_D4        to pins 20   !AT Added for minimum pin test.
assign IO_port_left_D5        to pins 21   !AT Added for minimum pin test.
assign IO_port_left_D6        to pins 22   !AT Added for minimum pin test.
assign IO_port_left_D7        to pins 23   !AT Added for minimum pin test.

assign Disable_pins_left      to pins 1,5,2

assign CE_bar_right           to pins 47
assign RW_bar_right           to pins 46
assign OE_bar_right           to pins 43
assign Add_right              to pins 33,34,35,36,37
assign Add_right              to pins 38,39,40,41,42

assign BUSY_bar_right         to pins 45
assign INT_bar_right          to pins 44

assign IO_port_right          to pins 32,31,30,29
assign IO_port_right          to pins 28,27,26,25
assign IO_port_right_D0       to pins 25   !AT Added for minimum pin test.
assign IO_port_right_D1       to pins 26   !AT Added for minimum pin test.
assign IO_port_right_D2       to pins 27   !AT Added for minimum pin test.
assign IO_port_right_D3       to pins 28   !AT Added for minimum pin test.
assign IO_port_right_D4       to pins 29   !AT Added for minimum pin test.
assign IO_port_right_D5       to pins 30   !AT Added for minimum pin test.
assign IO_port_right_D6       to pins 31   !AT Added for minimum pin test.
assign IO_port_right_D7       to pins 32   !AT Added for minimum pin test.

assign Disable_pins_right     to pins 47,43,46

inputs CE_bar_left,RW_bar_left
inputs OE_bar_left,Add_left
inputs CE_bar_right,RW_bar_right
inputs OE_bar_right,Add_right

outputs INT_bar_left,INT_bar_right
outputs BUSY_bar_left,BUSY_bar_right

bidirectional IO_port_left, IO_port_right
bidirectional IO_port_right_D0, IO_port_right_D1 !AT Added for min. pin test.
bidirectional IO_port_right_D2, IO_port_right_D3 !AT Added for min. pin test.
bidirectional IO_port_right_D4, IO_port_right_D5 !AT Added for min. pin test.
bidirectional IO_port_right_D6, IO_port_right_D7 !AT Added for min. pin test.
bidirectional IO_port_left_D0, IO_port_left_D1   !AT Added for min. pin test.
bidirectional IO_port_left_D2, IO_port_left_D3   !AT Added for min. pin test.
bidirectional IO_port_left_D4, IO_port_left_D5   !AT Added for min. pin test.
bidirectional IO_port_left_D6, IO_port_left_D7   !AT Added for min. pin test.

format hexadecimal IO_port_left,IO_port_right

family  TTL
power   VCC,GND

!*************      Backtrace Information  ***************************

trace IO_port_left to CE_bar_left,OE_bar_left,RW_bar_left,Add_left
trace INT_bar_left to Add_right,RW_bar_right,OE_bar_left
trace BUSY_bar_left to Add_left,Add_right,CE_bar_left,CE_bar_right

trace IO_port_right to CE_bar_right,OE_bar_right,RW_bar_right,Add_right
trace INT_bar_right to Add_right,RW_bar_right,OE_bar_right
trace BUSY_bar_right to Add_right,Add_right,CE_bar_right,CE_bar_right


!************     Disable information   ******************************

disable IO_port_left with Disable_pins_left to "1XX"
disable IO_port_left with Disable_pins_left to "011"

disable IO_port_right with Disable_pins_right to "1XX"
disable IO_port_right with Disable_pins_right to "011"

when Disable_pins_left is "0X0" inputs IO_port_left
when Disable_pins_left is "001" outputs IO_port_left
when Disable_pins_left is "1XX" inactive IO_port_left
when Disable_pins_left is "011" inactive IO_port_left

when Disable_pins_right is "0X0" inputs IO_port_right
when Disable_pins_right is "001" outputs IO_port_right
when Disable_pins_right is "1XX" inactive IO_port_right
when Disable_pins_right is "011" inactive IO_port_right

set load on groups  INT_bar_left, INT_bar_right    to pull up
set load on groups  BUSY_bar_left, BUSY_bar_right  to pull up

!warning "Pull-ups are required on the open drain outputs, BUSY_bar_left"
!warning "(pin 3),BUSY_bar_right(pin 45),INT_bar_right(pin 44), and "
!warning "INT_bar_left (pin 4) for the test to run."

warning "Pull-ups are also required in order to test the output enable pins."
warning "The pull-ups need to be placed on 16 pins, IO_port_left and"
warning "IO_port_right.  The two units that require these 16 pull-ups have"
warning "been commented out"

!**********************************************************************
!***********************   VECTOR   SECTION    ************************
!**********************************************************************

vector Set_values_left
   set OE_bar_left     to "1"
   set CE_bar_left     to "1"
   set RW_bar_left     to "1"
   set Add_left        to "0000000000"
end vector

vector Set_values_right
   set OE_bar_right    to "1"
   set CE_bar_right    to "1"
   set RW_bar_right    to "1"
   set Add_right       to "0000000000"
end vector

vector Keep_values_left
   set OE_bar_left     to "k"
   set CE_bar_left     to "k"
   set RW_bar_left     to "k"
   set Add_left        to "kkkkkkkkkk"
end vector

vector Keep_values_right
   set OE_bar_right    to "k"
   set CE_bar_right    to "k"
   set RW_bar_right    to "k"
   set Add_right       to "kkkkkkkkkk"
end vector

vector CE_bar_left_low
   initialize to Keep_values_left
   set CE_bar_left     to "0"
end vector

vector CE_bar_right_low
   initialize to Keep_values_right
   set CE_bar_right    to "0"
end vector

vector CE_bar_left_hi
   initialize to Keep_values_left
   set CE_bar_left     to "1"
end vector

vector CE_bar_right_hi
   initialize to Keep_values_right
   set CE_bar_right    to "1"
end vector

vector OE_bar_left_low
   initialize to Keep_values_left
   set OE_bar_left     to "0"
end vector

vector OE_bar_right_low
   initialize to Keep_values_right
   set OE_bar_right    to "0"
end vector

vector OE_bar_left_hi
   initialize to Keep_values_left
   set OE_bar_left     to "1"
end vector

vector OE_bar_right_hi
   initialize to Keep_values_right
   set OE_bar_right    to "1"
end vector

vector RW_bar_left_low
   initialize to Keep_values_left
   set RW_bar_left     to "0"
end vector

vector RW_bar_right_low
   initialize to Keep_values_right
   set RW_bar_right    to "0"
end vector

vector RW_bar_left_hi
   initialize to Keep_values_left
   set RW_bar_left     to "1"
end vector

vector RW_bar_right_hi
   initialize to Keep_values_right
   set RW_bar_right    to "1"
end vector

vector BUSY_bar_left_low
   initialize to Keep_values_left
   set BUSY_bar_left   to "0"
end vector

vector BUSY_bar_right_low
   initialize to Keep_values_right
   set BUSY_bar_right  to "0"
end vector

vector BUSY_bar_left_hi
   initialize to Keep_values_left
   set BUSY_bar_left   to "1"
end vector

vector BUSY_bar_right_hi
   initialize to Keep_values_right
   set BUSY_bar_right  to "1"
end vector

vector INT_bar_left_low
   initialize to Keep_values_left
   set INT_bar_left    to "0"
end vector

vector INT_bar_right_low
   initialize to Keep_values_right
   set INT_bar_right   to "0"
end vector

vector INT_bar_left_hi
   initialize to Keep_values_left
   set INT_bar_left    to "1"
end vector

vector INT_bar_right_hi
   initialize to Keep_values_right
   set INT_bar_right   to "1"
end vector

vector Add_left_0000000000
   initialize to Keep_values_left
   set Add_left        to "0000000000"
end vector

vector Add_left_0011001101
   initialize to Keep_values_left
   set Add_left        to "0011001101"
end vector

vector Add_left_0101010101
   initialize to Keep_values_left
   set Add_left        to "0101010101"
end vector

vector Add_left_1000001111
   initialize to Keep_values_left
   set Add_left        to "1010101010"
end vector

vector Add_left_1001001001
   initialize to Keep_values_left
   set Add_left        to "1001001001"
end vector

vector Add_left_1010101010
   initialize to Keep_values_left
   set Add_left        to "1010101010"
end vector

vector Add_left_1010110010
   initialize to Keep_values_left
   set Add_left        to "1010110010"
end vector

vector Add_left_1100000000
   initialize to Keep_values_left
   set Add_left        to "1100000000"
end vector

vector Add_left_1100110010
   initialize to Keep_values_left
   set Add_left        to "1100110010"
end vector


vector Add_left_1111111110
   initialize to Keep_values_left
   set Add_left        to "1111111110"
end vector

vector Add_left_1111111111
   initialize to Keep_values_left
   set Add_left        to "1111111111"
end vector

vector Add_right_0000000000
   initialize to Keep_values_right
   set Add_right       to "0000000000"
end vector

vector Add_right_0011001101
   initialize to Keep_values_right
   set Add_right       to "0011001101"
end vector

vector Add_right_0101010101
   initialize to Keep_values_right
   set Add_right       to "0101010101"
end vector

vector Add_right_1010101010
   initialize to Keep_values_right
   set Add_right       to "1010101010"
end vector

vector Add_right_1010110010
   initialize to Keep_values_right
   set Add_right       to "1010110010"
end vector

vector Add_right_1100110010
   initialize to Keep_values_right
   set Add_right       to "1100110010"
end vector

vector Add_right_1111111100
   initialize to Keep_values_right
   set Add_right       to "1111111100"
end vector

vector Add_right_1111111110
   initialize to Keep_values_right
   set Add_right       to "1111111110"
end vector

vector Add_right_1111111111
   initialize to Keep_values_right
   set Add_right       to "1111111111"
end vector

vector Left_port_drive_00
   initialize to Keep_values_left
   drive IO_port_left
   set IO_port_left    to "00"
end vector

vector Left_port_drive_55
   initialize to Keep_values_left
   drive IO_port_left
   set IO_port_left    to "55"
end vector

vector Left_port_drive_AA
   initialize to Keep_values_left
   drive IO_port_left
   set IO_port_left    to "AA"
end vector

vector Left_port_drive_CC
   initialize to Keep_values_left
   drive IO_port_left
   set IO_port_left    to "CC"
end vector

vector Left_port_drive_FF
   initialize to Keep_values_left
   drive IO_port_left
   set IO_port_left    to "FF"
end vector

vector Right_port_drive_00
   initialize to Keep_values_right
   drive IO_port_right
   set IO_port_right   to "00"
end vector

vector Right_port_drive_33
   initialize to Keep_values_right
   drive IO_port_right
   set IO_port_right   to "33"
end vector

vector Right_port_drive_55
   initialize to Keep_values_right
   drive IO_port_right
   set IO_port_right   to "55"
end vector

vector Right_port_drive_AA
   initialize to Keep_values_right
   drive IO_port_right
   set IO_port_right   to "AA"
end vector

vector Right_port_drive_CC
   initialize to Keep_values_right
   drive IO_port_right
   set IO_port_right   to "CC"
end vector

vector Right_port_drive_FF
   initialize to Keep_values_right
   drive IO_port_right
   set IO_port_right   to "FF"
end vector

vector Left_port_receive_00
   initialize to Keep_values_left
   receive IO_port_left
   set IO_port_left    to "00"
end vector

vector Left_port_receive_33
   initialize to Keep_values_left
   receive IO_port_left
   set IO_port_left    to "33"
end vector

vector Left_port_receive_55
   initialize to Keep_values_left
   receive IO_port_left
   set IO_port_left    to "55"
end vector

vector Left_port_receive_AA
   initialize to Keep_values_left
   receive IO_port_left
   set IO_port_left    to "AA"
end vector

vector Left_port_receive_CC
   initialize to Keep_values_left
   receive IO_port_left
   set IO_port_left    to "CC"
end vector

vector Left_port_receive_FF
   initialize to Keep_values_left
   receive IO_port_left
   set IO_port_left    to "FF"
end vector

vector Right_port_receive_00
   initialize to Keep_values_right
   receive IO_port_right
   set IO_port_right   to "00"
end vector

vector Right_port_receive_33
   initialize to Keep_values_right
   receive IO_port_right
   set IO_port_right   to "33"
end vector

vector Right_port_receive_55
   initialize to Keep_values_right
   receive IO_port_right
   set IO_port_right   to "55"
end vector

vector Right_port_receive_AA
   initialize to Keep_values_right
   receive IO_port_right
   set IO_port_right   to "AA"
end vector

vector Right_port_receive_CC
   initialize to Keep_values_right
   receive IO_port_right
   set IO_port_right   to "CC"
end vector

vector Right_port_receive_FF
   initialize to Keep_values_right
   receive IO_port_right
   set IO_port_right   to "FF"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector Left_port_drive_D0_0
   initialize to Keep_values_left
   drive IO_port_left_D0
   set IO_port_left_D0      to "0"
end vector

vector Left_port_drive_D0_1
   initialize to Keep_values_left
   drive IO_port_left_D0
   set IO_port_left_D0      to "1"
end vector

vector Right_port_drive_D0_0
   initialize to Keep_values_right
   drive IO_port_right_D0
   set IO_port_right_D0     to "0"
end vector

vector Right_port_drive_D0_1
   initialize to Keep_values_right
   drive IO_port_right_D0
   set IO_port_right_D0     to "1"
end vector

vector Left_port_receive_D0_0
   initialize to Keep_values_left
   receive IO_port_left_D0
   set IO_port_left_D0      to "0"
end vector

vector Left_port_receive_D0_1
   initialize to Keep_values_left
   receive IO_port_left_D0
   set IO_port_left_D0      to "1"
end vector

vector Right_port_receive_D0_0
   initialize to Keep_values_right
   receive IO_port_right_D0
   set IO_port_right_D0     to "0"
end vector

vector Right_port_receive_D0_1
   initialize to Keep_values_right
   receive IO_port_right_D0
   set IO_port_right_D0     to "1"
end vector

vector Left_port_drive_D1_0
   initialize to Keep_values_left
   drive IO_port_left_D1
   set IO_port_left_D1      to "0"
end vector

vector Left_port_drive_D1_1
   initialize to Keep_values_left
   drive IO_port_left_D1
   set IO_port_left_D1      to "1"
end vector

vector Right_port_drive_D1_0
   initialize to Keep_values_right
   drive IO_port_right_D1
   set IO_port_right_D1     to "0"
end vector

vector Right_port_drive_D1_1
   initialize to Keep_values_right
   drive IO_port_right_D1
   set IO_port_right_D1     to "1"
end vector

vector Left_port_receive_D1_0
   initialize to Keep_values_left
   receive IO_port_left_D1
   set IO_port_left_D1      to "0"
end vector

vector Left_port_receive_D1_1
   initialize to Keep_values_left
   receive IO_port_left_D1
   set IO_port_left_D1      to "1"
end vector

vector Right_port_receive_D1_0
   initialize to Keep_values_right
   receive IO_port_right_D1
   set IO_port_right_D1     to "0"
end vector

vector Right_port_receive_D1_1
   initialize to Keep_values_right
   receive IO_port_right_D1
   set IO_port_right_D1     to "1"
end vector

vector Left_port_drive_D2_0
   initialize to Keep_values_left
   drive IO_port_left_D2
   set IO_port_left_D2      to "0"
end vector

vector Left_port_drive_D2_1
   initialize to Keep_values_left
   drive IO_port_left_D2
   set IO_port_left_D2      to "1"
end vector

vector Right_port_drive_D2_0
   initialize to Keep_values_right
   drive IO_port_right_D2
   set IO_port_right_D2     to "0"
end vector

vector Right_port_drive_D2_1
   initialize to Keep_values_right
   drive IO_port_right_D2
   set IO_port_right_D2     to "1"
end vector

vector Left_port_receive_D2_0
   initialize to Keep_values_left
   receive IO_port_left_D2
   set IO_port_left_D2      to "0"
end vector

vector Left_port_receive_D2_1
   initialize to Keep_values_left
   receive IO_port_left_D2
   set IO_port_left_D2      to "1"
end vector

vector Right_port_receive_D2_0
   initialize to Keep_values_right
   receive IO_port_right_D2
   set IO_port_right_D2     to "0"
end vector

vector Right_port_receive_D2_1
   initialize to Keep_values_right
   receive IO_port_right_D2
   set IO_port_right_D2     to "1"
end vector

vector Left_port_drive_D3_0
   initialize to Keep_values_left
   drive IO_port_left_D3
   set IO_port_left_D3      to "0"
end vector

vector Left_port_drive_D3_1
   initialize to Keep_values_left
   drive IO_port_left_D3
   set IO_port_left_D3      to "1"
end vector

vector Right_port_drive_D3_0
   initialize to Keep_values_right
   drive IO_port_right_D3
   set IO_port_right_D3     to "0"
end vector

vector Right_port_drive_D3_1
   initialize to Keep_values_right
   drive IO_port_right_D3
   set IO_port_right_D3     to "1"
end vector

vector Left_port_receive_D3_0
   initialize to Keep_values_left
   receive IO_port_left_D3
   set IO_port_left_D3      to "0"
end vector

vector Left_port_receive_D3_1
   initialize to Keep_values_left
   receive IO_port_left_D3
   set IO_port_left_D3      to "1"
end vector

vector Right_port_receive_D3_0
   initialize to Keep_values_right
   receive IO_port_right_D3
   set IO_port_right_D3     to "0"
end vector

vector Right_port_receive_D3_1
   initialize to Keep_values_right
   receive IO_port_right_D3
   set IO_port_right_D3     to "1"
end vector

vector Left_port_drive_D4_0
   initialize to Keep_values_left
   drive IO_port_left_D4
   set IO_port_left_D4      to "0"
end vector

vector Left_port_drive_D4_1
   initialize to Keep_values_left
   drive IO_port_left_D4
   set IO_port_left_D4      to "1"
end vector

vector Right_port_drive_D4_0
   initialize to Keep_values_right
   drive IO_port_right_D4
   set IO_port_right_D4     to "0"
end vector

vector Right_port_drive_D4_1
   initialize to Keep_values_right
   drive IO_port_right_D4
   set IO_port_right_D4     to "1"
end vector

vector Left_port_receive_D4_0
   initialize to Keep_values_left
   receive IO_port_left_D4
   set IO_port_left_D4      to "0"
end vector

vector Left_port_receive_D4_1
   initialize to Keep_values_left
   receive IO_port_left_D4
   set IO_port_left_D4      to "1"
end vector

vector Right_port_receive_D4_0
   initialize to Keep_values_right
   receive IO_port_right_D4
   set IO_port_right_D4     to "0"
end vector

vector Right_port_receive_D4_1
   initialize to Keep_values_right
   receive IO_port_right_D4
   set IO_port_right_D4     to "1"
end vector

vector Left_port_drive_D5_0
   initialize to Keep_values_left
   drive IO_port_left_D5
   set IO_port_left_D5      to "0"
end vector

vector Left_port_drive_D5_1
   initialize to Keep_values_left
   drive IO_port_left_D5
   set IO_port_left_D5      to "1"
end vector

vector Right_port_drive_D5_0
   initialize to Keep_values_right
   drive IO_port_right_D5
   set IO_port_right_D5     to "0"
end vector

vector Right_port_drive_D5_1
   initialize to Keep_values_right
   drive IO_port_right_D5
   set IO_port_right_D5     to "1"
end vector

vector Left_port_receive_D5_0
   initialize to Keep_values_left
   receive IO_port_left_D5
   set IO_port_left_D5      to "0"
end vector

vector Left_port_receive_D5_1
   initialize to Keep_values_left
   receive IO_port_left_D5
   set IO_port_left_D5      to "1"
end vector

vector Right_port_receive_D5_0
   initialize to Keep_values_right
   receive IO_port_right_D5
   set IO_port_right_D5     to "0"
end vector

vector Right_port_receive_D5_1
   initialize to Keep_values_right
   receive IO_port_right_D5
   set IO_port_right_D5     to "1"
end vector

vector Left_port_drive_D6_0
   initialize to Keep_values_left
   drive IO_port_left_D6
   set IO_port_left_D6      to "0"
end vector

vector Left_port_drive_D6_1
   initialize to Keep_values_left
   drive IO_port_left_D6
   set IO_port_left_D6      to "1"
end vector

vector Right_port_drive_D6_0
   initialize to Keep_values_right
   drive IO_port_right_D6
   set IO_port_right_D6     to "0"
end vector

vector Right_port_drive_D6_1
   initialize to Keep_values_right
   drive IO_port_right_D6
   set IO_port_right_D6     to "1"
end vector

vector Left_port_receive_D6_0
   initialize to Keep_values_left
   receive IO_port_left_D6
   set IO_port_left_D6      to "0"
end vector

vector Left_port_receive_D6_1
   initialize to Keep_values_left
   receive IO_port_left_D6
   set IO_port_left_D6      to "1"
end vector

vector Right_port_receive_D6_0
   initialize to Keep_values_right
   receive IO_port_right_D6
   set IO_port_right_D6     to "0"
end vector

vector Right_port_receive_D6_1
   initialize to Keep_values_right
   receive IO_port_right_D6
   set IO_port_right_D6     to "1"
end vector

vector Left_port_drive_D7_0
   initialize to Keep_values_left
   drive IO_port_left_D7
   set IO_port_left_D7      to "0"
end vector

vector Left_port_drive_D7_1
   initialize to Keep_values_left
   drive IO_port_left_D7
   set IO_port_left_D7      to "1"
end vector

vector Right_port_drive_D7_0
   initialize to Keep_values_right
   drive IO_port_right_D7
   set IO_port_right_D7     to "0"
end vector

vector Right_port_drive_D7_1
   initialize to Keep_values_right
   drive IO_port_right_D7
   set IO_port_right_D7     to "1"
end vector

vector Left_port_receive_D7_0
   initialize to Keep_values_left
   receive IO_port_left_D7
   set IO_port_left_D7      to "0"
end vector

vector Left_port_receive_D7_1
   initialize to Keep_values_left
   receive IO_port_left_D7
   set IO_port_left_D7      to "1"
end vector

vector Right_port_receive_D7_0
   initialize to Keep_values_right
   receive IO_port_right_D7
   set IO_port_right_D7     to "0"
end vector

vector Right_port_receive_D7_1
   initialize to Keep_values_right
   receive IO_port_right_D7
   set IO_port_right_D7     to "1"
end vector

!**********************************************************************
!********************  SUBROUTINE   SECTION     ***********************
!**********************************************************************

sub Read_left(Address,Data)
   execute RW_bar_left_hi
   execute Address
   execute CE_bar_left_low
   execute OE_bar_left_low
   execute Data
   execute CE_bar_left_hi
   execute OE_bar_left_hi
end sub

sub Read_right(Address,Data)
   execute RW_bar_right_hi
   execute Address
   execute CE_bar_right_low
   execute OE_bar_right_low
   execute Data
   execute CE_bar_right_hi
   execute OE_bar_right_hi
end sub

sub Write_left(Address,Data)
   execute OE_bar_left_low
   execute Address
   execute CE_bar_left_low
   execute RW_bar_left_low
   execute Data
   execute RW_bar_left_hi
   execute CE_bar_left_hi
   execute OE_bar_left_hi
end sub

sub Write_right(Address,Data)
   execute OE_bar_right_low
   execute Address
   execute CE_bar_right_low
   execute RW_bar_right_low
   execute Data
   execute RW_bar_right_hi
   execute CE_bar_right_hi
   execute OE_bar_right_hi
end sub

!**********************************************************************
!*************************  UNIT   SECTION    *************************
!**********************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit   "awaretest Left D0 Test"

   execute Set_values_left

   call Write_left(Add_left_0000000000,Left_port_drive_D0_0)
   call Read_left(Add_left_0000000000,Left_port_receive_D0_0)

   call Write_left(Add_left_0000000000,Left_port_drive_D0_1)
   call Read_left(Add_left_0000000000,Left_port_receive_D0_1)

end unit

unit   "awaretest Left D1 Test"

   execute Set_values_left

   call Write_left(Add_left_0000000000,Left_port_drive_D1_0)
   call Read_left(Add_left_0000000000,Left_port_receive_D1_0)

   call Write_left(Add_left_0000000000,Left_port_drive_D1_1)
   call Read_left(Add_left_0000000000,Left_port_receive_D1_1)

end unit

unit   "awaretest Left D2 Test"

   execute Set_values_left

   call Write_left(Add_left_0000000000,Left_port_drive_D2_0)
   call Read_left(Add_left_0000000000,Left_port_receive_D2_0)

   call Write_left(Add_left_0000000000,Left_port_drive_D2_1)
   call Read_left(Add_left_0000000000,Left_port_receive_D2_1)

end unit

unit   "awaretest Left D3 Test"

   execute Set_values_left

   call Write_left(Add_left_0000000000,Left_port_drive_D3_0)
   call Read_left(Add_left_0000000000,Left_port_receive_D3_0)

   call Write_left(Add_left_0000000000,Left_port_drive_D3_1)
   call Read_left(Add_left_0000000000,Left_port_receive_D3_1)

end unit

unit   "awaretest Left D4 Test"

   execute Set_values_left

   call Write_left(Add_left_0000000000,Left_port_drive_D4_0)
   call Read_left(Add_left_0000000000,Left_port_receive_D4_0)

   call Write_left(Add_left_0000000000,Left_port_drive_D4_1)
   call Read_left(Add_left_0000000000,Left_port_receive_D4_1)

end unit

unit   "awaretest Left D5 Test"

   execute Set_values_left

   call Write_left(Add_left_0000000000,Left_port_drive_D5_0)
   call Read_left(Add_left_0000000000,Left_port_receive_D5_0)

   call Write_left(Add_left_0000000000,Left_port_drive_D5_1)
   call Read_left(Add_left_0000000000,Left_port_receive_D5_1)

end unit

unit   "awaretest Left D6 Test"

   execute Set_values_left

   call Write_left(Add_left_0000000000,Left_port_drive_D6_0)
   call Read_left(Add_left_0000000000,Left_port_receive_D6_0)

   call Write_left(Add_left_0000000000,Left_port_drive_D6_1)
   call Read_left(Add_left_0000000000,Left_port_receive_D6_1)

end unit

unit   "awaretest Left D7 Test"

   execute Set_values_left

   call Write_left(Add_left_0000000000,Left_port_drive_D7_0)
   call Read_left(Add_left_0000000000,Left_port_receive_D7_0)

   call Write_left(Add_left_0000000000,Left_port_drive_D7_1)
   call Read_left(Add_left_0000000000,Left_port_receive_D7_1)

end unit

unit   "awaretest Right D0 Test"

   execute Set_values_Right

   call Write_Right(Add_Right_0000000000,Right_port_drive_D0_0)
   call Read_Right(Add_Right_0000000000,Right_port_receive_D0_0)

   call Write_Right(Add_Right_0000000000,Right_port_drive_D0_1)
   call Read_Right(Add_Right_0000000000,Right_port_receive_D0_1)

end unit

unit   "awaretest Right D1 Test"

   execute Set_values_Right

   call Write_Right(Add_Right_0000000000,Right_port_drive_D1_0)
   call Read_Right(Add_Right_0000000000,Right_port_receive_D1_0)

   call Write_Right(Add_Right_0000000000,Right_port_drive_D1_1)
   call Read_Right(Add_Right_0000000000,Right_port_receive_D1_1)

end unit

unit   "awaretest Right D2 Test"

   execute Set_values_Right

   call Write_Right(Add_Right_0000000000,Right_port_drive_D2_0)
   call Read_Right(Add_Right_0000000000,Right_port_receive_D2_0)

   call Write_Right(Add_Right_0000000000,Right_port_drive_D2_1)
   call Read_Right(Add_Right_0000000000,Right_port_receive_D2_1)

end unit

unit   "awaretest Right D3 Test"

   execute Set_values_Right

   call Write_Right(Add_Right_0000000000,Right_port_drive_D3_0)
   call Read_Right(Add_Right_0000000000,Right_port_receive_D3_0)

   call Write_Right(Add_Right_0000000000,Right_port_drive_D3_1)
   call Read_Right(Add_Right_0000000000,Right_port_receive_D3_1)

end unit

unit   "awaretest Right D4 Test"

   execute Set_values_Right

   call Write_Right(Add_Right_0000000000,Right_port_drive_D4_0)
   call Read_Right(Add_Right_0000000000,Right_port_receive_D4_0)

   call Write_Right(Add_Right_0000000000,Right_port_drive_D4_1)
   call Read_Right(Add_Right_0000000000,Right_port_receive_D4_1)

end unit

unit   "awaretest Right D5 Test"

   execute Set_values_Right

   call Write_Right(Add_Right_0000000000,Right_port_drive_D5_0)
   call Read_Right(Add_Right_0000000000,Right_port_receive_D5_0)

   call Write_Right(Add_Right_0000000000,Right_port_drive_D5_1)
   call Read_Right(Add_Right_0000000000,Right_port_receive_D5_1)

end unit

unit   "awaretest Right D6 Test"

   execute Set_values_Right

   call Write_Right(Add_Right_0000000000,Right_port_drive_D6_0)
   call Read_Right(Add_Right_0000000000,Right_port_receive_D6_0)

   call Write_Right(Add_Right_0000000000,Right_port_drive_D6_1)
   call Read_Right(Add_Right_0000000000,Right_port_receive_D6_1)

end unit

unit   "awaretest Right D7 Test"

   execute Set_values_Right

   call Write_Right(Add_Right_0000000000,Right_port_drive_D7_0)
   call Read_Right(Add_Right_0000000000,Right_port_receive_D7_0)

   call Write_Right(Add_Right_0000000000,Right_port_drive_D7_1)
   call Read_Right(Add_Right_0000000000,Right_port_receive_D7_1)

end unit


!This unit checks the left port only by writing to and reading from
!two different addresses.

unit "Check left ports"

   execute Set_values_left

   call Write_left(Add_left_0101010101,Left_port_drive_AA)
   call Write_left(Add_left_1100000000,Left_port_drive_55)
   call Write_left(Add_left_1010101010,Left_port_drive_00)

   call Read_left(Add_left_0101010101,Left_port_receive_AA)
   call Read_left(Add_left_1100000000,Left_port_receive_55)
   call Read_left(Add_left_1010101010,Left_port_receive_00)

end unit

!This unit checks the right port only by writing to and reading from
!two distinct addresses.

unit "Check right port"

   execute Set_values_right

   call Write_right(Add_right_1100110010,Right_port_drive_33)
   call Write_right(Add_right_0011001101,Right_port_drive_CC)
   call Write_right(Add_right_1111111100,Right_port_drive_00)

   call Read_right(Add_right_1100110010,Right_port_receive_33)
   call Read_right(Add_right_0011001101,Right_port_receive_CC)
   call Read_right(Add_right_1111111100,Right_port_receive_00)

end unit

!In the next unit, the data is written to the core memory from the
!left side and accessed through the right side.

unit "Write left, read right"

   execute Set_values_left
   execute Set_values_right

   call Write_left(Add_left_0101010101,Left_port_drive_AA)
   call Write_left(Add_left_1010101010,Left_port_drive_55)

   call Read_Right(Add_Right_0101010101,Right_port_receive_AA)
   call Read_Right(Add_Right_1010101010,Right_port_receive_55)

end unit

!Now, the right side of the RAM is written to and the left side
!accesses the information.

unit "Write right, read left"

   call Write_right(Add_right_1100110010,Right_port_drive_33)
   call Write_right(Add_right_0011001101,Right_port_drive_CC)

   call Read_left(Add_left_1100110010,Left_port_receive_33)
   call Read_left(Add_left_0011001101,Left_port_receive_CC)

end unit

!NOTE, the next two units require a total of 16 pull-ups in order
!to function properly.  If these units are NOT executed, then
!the output enable pins (pins 5,43) will NOT be completely tested!!!

!unit "Test left output enable"

!This unit requires pull-ups on the left I/O lines pins 16 through 23.

!   execute Set_values_left
!   call Write_left(Add_left_1001001001,Left_port_drive_00)
!   execute RW_bar_left_hi
!   execute Add_left_1001001001
!   execute CE_bar_left_low
!   execute OE_bar_left_hi
!   execute Left_port_receive_FF
!end unit

!unit "Test right output enable"
!
!!This unit requires pull-ups on the right I/O lines pins 25 thru 32.
!
!   execute Set_values_right
!   call Write_right(Add_right_1001001001,Right_port_drive_00)
!   execute RW_bar_left_hi
!   execute Add_left_1001001001
!   execute CE_bar_left_low
!   execute OE_bar_left_hi
!   execute Right_port_receive_FF
!end unit

!This unit tests the Chip enable pin for the left side of the device.

unit "Test left Chip Enable"

   execute Set_values_left
   execute Add_left_1010101010
   execute RW_bar_left_low
   execute CE_bar_left_low
   execute Left_port_drive_AA
   execute RW_bar_left_hi
   execute CE_bar_left_hi
   execute Add_left_1010101010
   execute RW_bar_left_low
   execute CE_bar_left_hi
   execute Left_port_drive_55
   execute RW_bar_left_hi
   call Read_left(Add_left_1010101010,Left_port_receive_AA)

end unit

!This unit tests the right Chip enable pin of the device.

unit "Test right Chip Enable"

   execute Set_values_right
   execute Add_right_1010101010
   execute RW_bar_right_low
   execute CE_bar_right_low
   execute Right_port_drive_AA
   execute RW_bar_right_hi
   execute CE_bar_right_hi
   execute Add_right_1010101010
   execute RW_bar_right_low
   execute CE_bar_right_hi
   execute Right_port_drive_55
   execute RW_bar_right_hi
   call Read_right(Add_right_1010101010,Right_port_receive_AA)

end unit

!The BUSY_bar pins are used to moderate bus contention.  The side that
!is accessed first wins, and the opposite side puts out a low signal
!on the BUSY line until the winning side has finished its cycle.  Then
!the losing side can continue its function.

unit "Test BUSY_left"

   execute Set_values_right
   execute Set_values_left

   execute OE_bar_right_low
   execute OE_bar_left_low
   execute CE_bar_right_low
   execute CE_bar_left_low
   execute Add_right_1010110010
   execute Add_left_1010110010
   homingloop 10 times
      execute BUSY_bar_left_low     exit if pass
   end homingloop

   execute RW_bar_right_low
   execute Right_port_drive_55
   execute RW_bar_right_hi
   execute CE_bar_right_hi
   execute OE_bar_right_hi
   homingloop 20 times
      execute BUSY_bar_left_hi      exit if pass
   end homingloop

   homingloop 20 times
     execute Left_port_receive_55  exit if pass
   end homingloop
   execute Keep_values_left
   execute CE_bar_left_hi
   execute OE_bar_left_hi
end unit

unit "Test BUSY_right"

   execute Set_values_left
   execute Set_values_right
   execute OE_bar_left_low
   execute OE_bar_right_low
   execute CE_bar_left_low
   execute CE_bar_right_low
   execute Add_left_1010101010
   execute Add_right_1010101010
   homingloop 10 times
      execute BUSY_bar_right_low    exit if pass
   end homingloop

   execute RW_bar_left_low
   execute Left_port_drive_CC
   execute RW_bar_left_hi
   execute CE_bar_left_hi
   execute OE_bar_left_hi
   homingloop 20 times
      execute BUSY_bar_right_hi   exit if pass
   end homingloop
   homingloop 20 times
      execute Right_port_receive_CC      exit if pass
   end homingloop
end unit

!The interrupt line is used so that one side can interrupt the other
!by trying to access a specific address and then attempting to start
!a write cycle.  When this occurs, the opposite side sends out a low
!signal on the INT_bar line until the side that was interrupted resets
!itself by sending out that same address that started the interrupt and
!also enabling its output enable and chip enable lines.


unit "Test INT_left"
   execute Set_values_left
   execute Set_values_right
   execute CE_bar_left_low
   execute CE_bar_right_low
   execute Add_right_1111111110
   execute RW_bar_right_low
   homingloop 10 times
      execute INT_bar_left_low  exit if pass
   end homingloop
   execute RW_bar_left_hi
   execute Add_left_1111111110
   execute CE_bar_left_low
   execute OE_bar_left_low
   homingloop 20 times
      execute INT_bar_left_hi   exit if pass
   end homingloop

end unit

unit "Test INT_right"

   execute Set_values_left
   execute Set_values_right
   execute CE_bar_left_low
   execute CE_bar_right_low
   execute Add_left_1111111111
   execute RW_bar_left_low
   homingloop 10 times
      execute INT_bar_right_low   exit if pass
   end homingloop
   execute RW_bar_right_hi
   execute Add_right_1111111111
   execute CE_bar_right_low
   execute OE_bar_right_low
   homingloop 20 times
      execute INT_bar_right_hi    exit if pass
   end homingloop

end unit

!!!end of test!!!