Agilent recommends an 866 MHz, Intel® Celeron™ or AMD K6-II equivalent PC with 320 MB RAM minimum, running Windows® 2000 Professional or Windows XP Professional.
Version 3.67 of the logic analyzer application requires Windows 2000 Professional platforms to be at Service Pack 3 or higher.
Version 3.67 of the logic analyzer application software supports Windows XP Professional Service Pack 2.
Install the application: Select Start, Run..., SetupLA03670000.exe, OK. (The Agilent Logic Analyzer icon is placed on your desktop once setup is complete.)
Start the application: Double click the Agilent Logic Analyzer icon on your desktop.
View logic analyzer data: If you do not have 16900, 16800, or 1680/90 series logic analyzer hardware to connect to, or you do not have data captured from one of the supported logic analyzers, select "Edit, Options, Create Data When Offline".
Version 03.67 of the logic analyzer application includes these changes:
Import Oscilloscope Data and View Offline
MSO digital channel import — the Add External Oscilloscope wizard now sets up an external oscilloscope module that can import digital channel data from mixed-signal oscilloscopes as well as analog channel data. Also, external oscilloscope modules can now be correlated with split logic analyzer modules.
View Oscilloscope Data Offline — the oscilloscope data format (.bin) to logic analyzer format (.alb) converter converts oscilloscope data to .alb format. Once converted, oscilloscope data can be imported and viewed in the Agilent Logic Analyzer application. To run the converter, choose Start>All Programs>Agilent Logic Analyzer>Utilities>Scope BIN to ALB Translator from the Windows Start menu.
Pattern Generator Enhancements:
Find instructions or vectors in the sequence.
Use macro, loop, and comment instructions when importing vectors from CSV format files (exporting to CSV format files still gives compiled sequences).
Change the colors associated with instructions and macros.
External Protocol Analyzer Time Correlation — the correlation software now supports the N5319A interconnect cable that connects between the N5306A protocol analyzer module’s Inter-Module (x16) port and a 16900 Series logic analysis system multiframe connector to provide more flexible cross-triggering via flags.
B4655A FPGA Dynamic Probe Feature Additions — the B4655A now supports connecting to JTAG cables on remote PCs or logic analysis systems. Also, Spartan-3 FPGAs are now supported.
Status Dialog Enhancements (displays the logic analysis system status):
More information is now shown in the columns of the display and you can choose which columns are displayed.
Added the ability to look at the trigger timestamp, flags, timers, and counters.
Add or Remove Logic Analyzer Software tool — in order to ensure you have access to all of the features and capabilities available for your logic analyzer, Agilent recommends using the Add or Remove Logic Analyzer Software tool. The tool copies all application software to the hard drive for easy access. Installation will occur when you choose to install an application or when an application is requested in Demo Center. To access the tool, simply insert the logic analyzer application software CD into the CD drive for the logic analyzer.
Analog Properties — a property has been added within the Analog Properties dialog to turn Y scaling on/off.
The available menu resources have been increased to eliminate error messages when loading large ALA files.
The ARM decoder has been modified to properly handle vector floating point instructions: FLDMD, FLDMS, FSTMD, FSTMS.
The MXC decoder properly handles chip selects and provides correct addresses.
The P2L gateway has been modified to cross trigger appropriately between the logic analyzer and protocol analyzer when a module is installed in slot A.
Probes.XML — For the 16760A module, the Probes.XML file could have two versions of each probe — one with the half-channel adapter and one without the half-channel adapter. A new check has been put in place to scan the probe type for the E5386A half-channel adapter.
XML file changes:
A parameter has been added to the pattern model querycommand function that allows the user to tell the pattern model to not write out the module name as an attribute. This capability is used when creating triggers for use across multiple configuration files. The module name is still written out in all other cases. The only case where it is not written out is when generating the trigger specification. To fix existing XML files, edit the file and remove all "Module=" attributes.
Symbols:
ALB files now have the ability to include simple symbols. Symbols that are loaded through the ALB are also persisted in the XML file.
Symbols are preserved when loading an xml setup for a virtual analyzer.
Import:
When using the Data Import Tool, the correct value is written to the upper byte when a bus label spans a byte.
A symbol menu option has been added to the setup menu. A new SYMBOL keyword has been added to ALB files so that symbols can be placed in the ALB and loaded.
When importing pattern generator CSV ASCII files, special characters like /, [, ], (, and ) are now permitted. The exceptions are single and double quotes (',").
Version 03.65 of the logic analyzer application includes these new capabilities and modifications:
16951B logic analyzer module support — The 16951B offers:
B4641A Protocol Development Kit — The B4641A software lets you edit and create protocol description files in order to decode, display and trigger on customized packet data. The customized packet data is displayed in the Packet Viewer. The Packet Viewer simultaneously displays packet summaries and detailed information for each packet.
Specify Fixed Time Units for the Time Column in Listing — In the Listing window, you can display time column values with a fixed unit. Right click on the Time column and select "Properties...". Check Use Fixed Unit, then select the desired time unit from the dropdown list.
PCI Express Protocol Decoder and Event Editor:
Filter Tool — When loading an XML filter favorite into a new filter, a dialog will display if the bus/signal names available from the module are not the same as those used in the filter favorite.
Front Panel Operation:
Logic Analyzer Service — The logic analyzer service shutdown sequence has been re-ordered to appropriately set the status and re-initialization of a multiframe system.
Switching to online mode — Saving a file online that has just been saved in offline mode saves correctly.
Pattern Generator Programming — The pattern generator Find function call now accepts both operators and strings for all variations of the "Present" parameter.
Version 03.60 of the logic analyzer application includes these new capabilities and modifications:
16901A 2-slot modular logic analysis system support — The 16901A offers:
16950B logic analyzer module support — The 16950B offers:
B4656A FPGA Dynamic Probe for Altera — The B4656A FPGA dynamic probe software gives you easy access to signals internal to Altera FPGAs and provides significant productivity improvements when debugging FPGA designs. The dynamic probe lets you view up to 256 internal probe points for each external pin dedicated to debug. It measures new groups of internal signals in seconds without design changes. It also eliminates error-prone and time-consuming tasks with automated signal/bus name importing from the FPGA design software to the logic analyzer.
Time Correlation to Agilent E2960 Series protocol analyzers for PCI Express — Time-correlate PCI Express bus activity with the activity from other devices in your digital system:
Cross-trigger and make time-correlated measurements, using tracking markers, between an external protocol analyzer and a logic analyzer.
Default de-skew values are established for the specific logic analyzer and protocol analyzer connection or you can manually enter de-skew values, if desired.
Multiple PCI Express protocol analyzers can be time-correlated to a single logic analyzer.
Requires LAN and an N5313A cable to establish the link between the logic analyzer and PCI Express protocol analyzer.
Access this capability from Setup>Add External Protocol Analyzer.
Works with Agilent N5306A protocol analyzer modules for PCI Express Gen 2 and N5305A protocol analyzer modules for PCI Express Gen 1.
Demo Center additions — Learn more about new features and capabilities supported by your logic analyzer.
"Read-Only" capability for licensed tools in offline mode — Easily share and view data files in offline mode. Some application software (inverse assemblers, packet decoders, etc.) requires a license to enable the software's capability. When you make measurements on a logic analyzer with licenses, configuration files saved in the ALA format can be viewed "read-only" by others in offline mode without having licenses for the tools used in the configuration. Licenses are required to go online or to add any licensed tools, windows, etc.
Packet Viewer — The Packet Viewer is removed from the Overview tab when one or more packet decoders connected to it are disabled.
VBAView>Distribution Sample…
The Distribution macro has been updated to work with non-hex based symbols.
Bus/signal names from analysis tools, whether passed through from a module or created new in the tool, can now be used by the Distribution Sample macro.
Symbol reader / Source correlation:
The symbol reader has been updated to work with COFF2 files with section names > 8 characters.
Source correlation allows the user to specify a local path to use when searching for source files. In the instance where multiple files have the same name but different paths, you can find all files with the same name, without having to specify all possible paths, by changing the .ini file to accept a path change command of the form:
#SourceFilePathChange="Orig_path;New_path"
Message Dialogs:
In some instances, the following message is displayed when using the touch screen: "This is an evaluation version of UPDD. Click OK to continue." The evaluation and released versions of the touch screen driver provide equivalent functionality. When the touch screen driver is updated in the next version of the recovery software, this dialog will no longer occur.
The Filter tool will display a warning dialog when bus/signal names requested in the filter definition are not available to the filter tool. This may occur in a configuration file when saving a Filter Favorite from one filter tool that has access to bus/signals names to another filter tool that does not have access to the same bus/signal names.
Loading Configuration Files — Trigger Arming and Flags allocation is delayed until the load of a configuration file is complete.
Split Analyzers — If you choose to disable one analyzer in a split analyzer configuration, both analyzers will be disabled. Any Arming between the split analyzers and other modules in the system will also be disabled.
Multiframe — Multiframe systems running on versions 3.56 or 3.57.0000 should be updated to version 03.57.1000 or higher. Once updated, cycle power on the frames in the multiframe configuration to update the system FPGAs with the latest firmware.
Version 03.55 of the logic analyzer application includes these changes:
E9524A MicroBlaze Trace Toolset — Updated the inverse assembler to support MicroBlaze Version 5.
Symbol reader modifications:
When correlating the logic analyzer trace to source code, the absolute symbol file path is used first and then, if the symbol file is not found there, the search is done in the same folder as the logic analyzer .ala configuration file. This addition to the search capability works with .ala files and occurs upon a load.
The symbol reader has been updated to ignore zero size functions from the dwarf section of an Elf/Dwarf symbol file. An option exists to allow zero size Dwarf section functions to be accepted. (Note: Zero size functions have always been ignored in the Elf section and the user must enter an option to enable the zero size Elf section functions to be shown.)
The XML properly sets the global timer/counter variables for COM control of logic analyzer settings.
Multiple analyzers can now be disabled, on-line or off-line.
Fixed problem where some logic analysis system frames would not initialize on power-up.
Fixed connection errors when going online with some logic analysis systems.
Version 03.50 of the logic analyzer application includes these changes:
16800 Series portable logic analyzer support — With the 16800 series portable logic analyzers, Agilent delivers an exclusive combination of logic analysis and pattern generation, application software, and innovative probing that will make you more productive and enable you to quickly overcome your toughest digital debug challenges…all at a price that will fit your budget.
The 16800 series offers eight models with:
Online help system is available in Chinese — select Help > Help Language > Chinese.
Packet Viewer window and Event Editor — The Packet Viewer is a display window that is customized for the protocol family being decoded by the Packet Decoder tool. To optimize protocol viewing and analysis you can simultaneously view summarized and detailed information. The upper pane in the window displays decoded packets and fields in columns while the tabs in the lower pane provide packet details, header, payload, and lane information.
The Packet Viewer supports: PCI Express, Serial ATA, Serial Attached SCSI, InfiniBand, Advanced Switching Interface (ASI), Parallel Rapid IO, and SPI 4.2 (Pos PHY L4).
To make your protocol measurements easier, you can specify the logic analyzer trigger sequence using packets. The packet Event Editor allows you to:
E9524A MicroBlaze Trace Toolset — Easily trace MicroBlaze software execution at the assembly or source level. The toolset combines the capabilities of a MicroBlaze inverse assembler with a specialized trace core that simplifies measurement setup and reduces the number of pins dedicated to debug.
The inverse assembler allows a choice of instruction-side and/or data-side decoding, and can accommodate variations of bus widths and different combinations of the signals to allow maximum flexibility. MicroBlaze execution is tracked deterministically, even when cache is enabled, since captured signals are routed from the execution stage of the MicroBlaze pipeline.
B4602A Signal Extractor Tool — You can use the Signal Extractor tool to extract data from one input bus/signal and place it on multiple output buses/signals. This is useful for extracting I and Q data from simple serial protocols or re-multiplexing high-speed digital data that has been de-multiplexed onto additional logic analyzer channels. The extractor algorithm file specifies the output buses/signals and how the data should be extracted.
Graphical Trigger Overview — The graphical trigger overview shows the trigger sequence levels and goto sequence arrows. It’s animated while the trigger is active. It also provides status information for occurrence counters, global counters, flags, and timers. It can be accessed either through the status button on the main application or through each module’s pull down menu from the overview.
10 MHz Clock In to keep logic analyzer and oscilloscope in sync — If you see correlation drift in long acquisitions as markers get farther away from the trigger, you can synchronize the logic analyzer and oscilloscope traces by using the logic analysis system’s 10 MHz CLOCK IN input (if present).
The logic analysis system’s CLOCK IN input is auto-sensing at power up; therefore, to use this input:
Demo Center — Learn more about your logic analyzer’s features and capabilities. From the Agilent Logic Analyzer application's main menu, choose Help>Show Demo…. Use the left pane to navigate to the feature demonstration you want to view. The Expand and Collapse buttons affect the feature hierarchy tree. Select the feature you want to learn about by clicking it. Information about the feature appears in the right pane.
Rename the bits of a bus — When a bus is expanded in the Waveform display window, you can rename the individual bits that make up the bus.
Insert separator in waveform — To add distance between waveforms, you can add separator rows to the Waveform display window. In the Waveform display window, right-click in the Bus/Signal column; then, choose Insert Separator. Separator rows can be sized, colored, re-arranged, and deleted just like bus/signal waveform rows.
Quick access to default Agilent configuration folders — all Agilent configuration folders have been moved to a common folder on the desktop.
Chat Dialog — The Chat dialog lets you determine if a remote system is available by entering and sending messages to other logic analyzer system users.
User Data Import of binary .alb — You can import external data into the logic analysis system from module binary (ALB) format files as well as module CSV format text files.
Update to Agilent IO Libraries — the IO Libraries have been updated to version 14.2.
Frame/Module Information Dialog — Displays detailed information about the logic analysis system, including: the frame, measurement hardware, module upgrade information (memory depth or state speed), software version, host IP address, host name, whether or not the frame is password protected from remote-access, etc.
Addition to Contributed Files: Start > Programs > Agilent Logic Analyzer > Contributed Files
Processor/Bus/Protocol support additions:
Addition of "Export" RPI command.
Arm In from External trigger is properly initialized.
LAN communication updated to eliminate any possible race conditions.
Version 03.30 of the logic analyzer application includes the following for 1680, 1690, and 16900 series logic analyzers (unless noted otherwise):
View Scope: Responsive, integrated oscilloscope and logic analyzer waveform display without any custom cabling or additional cost. Provides time-correlated measurements across analog and digital domains. Includes:
Direct connection of the logic analyzer and oscilloscope.
Automated set up with logic analyzer and oscilloscope waveforms integrated into a single logic analyzer display.
Cross trigger in either direction between the logic analyzer and oscilloscope.
Time-correlated tracking markers.
External oscilloscope correlation works with the following oscilloscopes, set up for remote control via LAN:
System Performance Improvements:
Time-to-first measurement and follow-on measurements have been dramatically reduced through changes to module initialization routines. Multiple modules and multi-frame configurations are now initialized in parallel. Module initialization only occurs on the first run unless user interface or setup changes require re-initialization.
Significantly faster oscilloscope waveform import and display achieved through accelerated data management algorithms. Import of 8M deep oscilloscope waveforms takes a matter of seconds.
Symbol management algorithm optimized for faster access of large symbol files. Use of wildcards improves symbol search.
Faster Overview window and overall GUI responsiveness due to optimizing updates to the Overview window. Updates occur when making trigger changes, enabling/disabling probes, modules, tools, or windows.
89600 Vector Signal Analysis compatibility: Includes support to link logic analyzer and 89600 VSA software. Perform time-domain, spectrum, and modulation quality analysis on digital baseband and IF signals. Analyze your signal as it changes from a train of perfect symbols to a signal with filtering, pre-distortion, re-sampling, or other potential sources of error.
B4630A MATLAB Connectivity and Analysis Package: Easily use your custom MATLAB routines in conjunction with data acquired from the logic analysis system. This licensed package contains these VBA macros and VbaView windows:
SendToMatLab VBA macro that sends logic analyzer data to MATLAB.
MatLab Analysis VbaView window that sends logic analyzer data to MATLAB for processing and displays the results in an XY scattergram chart.
FFT VbaView window that performs a Fast Fourier Transform on logic analyzer data and displays the results in a line chart.
B4610A Data Import Tool: Import external data into the logic analysis system and analyze it just like data acquired by logic analyzer modules. Import modules read data from a module CSV file and make it available to tools and display windows. Module CSV files can be created by external tools or saved from any module using the main menu's File>Export… command. Data import modules are a licensed feature. You can evaluate the data import capability on imported data limited to 16 rows without a license.
Contributed Files: Start > Programs > Agilent Logic Analyzer > Contributed Files
10b.gpa file: The 10.gpa file is a General-Purpose ASCII symbol file that displays hex byte values, character names, and disparity values for 8B/10B encoded values captured by the logic analyzer. You can edit the 10b.gpa file to show only the fields of interest.
Multi-module setup utility: The purpose of this macro is to efficiently set up multiple logic analyzer modules at one time. While all of these properties can be set up for each module one at a time, this macro allows users to quickly set multiple modules to the same values. The properties that can be set up from this dialog are:
B4655A FPGA Dymanic Probe: Upgraded JTAG drivers to match Xilinx ChipScope Pro 7.1i JTAG drivers.
B4607A Advanced Customization Environment Runtime Package additions and updates:
SendToExcel VBA macro that sends captured data to Microsoft Excel.
SendToPatternGeneratorModule VBA macro that sends captured data to a pattern generator module.
Timing Compare VbaView window that compares timing analyzer data with a specified tolerance (plus or minus a number of samples).
Extended the number of buckets for Distribution from 255 to 65535.
Progress dialog presents percent done information and provides ability to cancel current action.
Specify range by either time, markers, or sample number.
License Management: Implemented easier licensing management dialog with the flexibility of multiple licensing types to fit your work style.
Processor/Bus support additions:
Wildcard Search for Select Symbol dialog: The Select Symbol dialog has been updated to sort on any field and to perform a symbol search with or without wildcards (*,?). * (asterisk) represents zero or more characters. ? (question mark) represents a single character.
Data Offscreen indicator: Clicking on the indicator adjusts the display delay to the point in time where data is available.
External Application Setup dialog: Get easy access to other Windows applications within the logic analyzer application by adding, editing, and arranging items from the Tools>External Applications menu.
Analysis API Wizard: The wizard for creating your own inverse assemblers has been updated to work with Visual Studio Ver 7.0.
The scroll wheel now activates windows and changes focus.
A selection for ‘picoseconds’ has been added to the time label.
When selecting a valid file in the File>Save As… dialog, all fields from saved .ALA files are presented (Owner, Project, and Description).
Eye Scan runs in accumulate/repeat mode.
Updated the CDR settings of the N4219B SATA probe drivers to provide a cleaner eye to the probe receivers.
16700 Fast Binary Import:
16760 fast binary data, can be imported into the 16900-series logic analyzer application software.
Saving a 16900-series setup that includes 16700-series fast binary data with Timing Zoom data properly saves the Timing Zoom data.
Fixed calculation of the number of bytes per sample for fast binary import.
Symbol use with a .r converted inverse assembler operates correctly when repackaged.
Updated transitional timing to correctly capture and display narrow transitions.
The logic analyzer imports and displays oscilloscope data points without interpolation.
Protocol decode information is displayed correctly, eliminating duplicated decode information.
Zoom In correctly displays the requested timeframe.
Option for ‘Fixed Width’ added for .csv export of lister data.
InstallShield startup attribute has been changed to ‘normal’ instead of ‘maximize’ when creating all logic analyzer shortcuts.
Version 03.20 of the logic analyzer application includes the following for 1680, 1690, and 16900 series logic analyzers (unless noted otherwise):
16760A High-speed state/timing module support (16900 series only): Added support for the Agilent 16760A LVDS state/timing logic analysis module. The 16760A module supports differential and single-ended buses at state speeds up to 1.5 Gb/s.
B4601C Serial to Parallel Analysis Package: The Serial-to-Parallel analysis package is used to convert a serial data stream into parallel data words. Parallel data word width is selectable up to 128 bits and can be displayed in a variety of number bases. Advanced options let you:
Time-correlated measurements with Agilent 6000 Series oscilloscopes. Includes:
Scope waveform import: Oscilloscope support — Agilent 6000 Series, Infiniium 54800 Series, and DSO80000 Series. Provides the ability to…
B4655A FPGA dynamic probe feature additions:
Advanced Customization Environment feature additions:
Processor/Bus support additions:
Enabled floating/server licensing support for the following products:
Added the ability to disable modules. When you save .ala configurations, no data is saved for disabled modules. All Windows, Tools, and connections remain. Buses/signals from the disabled module are not available in the downstream windows and tools until the module is re-enabled.
Mice with scroll wheels and tilt wheels are now supported.
The 16720A pattern generator vectors are now saved in .xml as well as .ala files.
File, Export… now recalls the signals from the previous export. If a different source module/tool is selected, or if the signals used from the previous export have been deleted, the list will be populated with the default bus/signals from the current source.
A ConnectSystem object has been created to support file transfers to/from the host to the logic analyzer. See the COM Automation online help documentation for more details.
The utility for translating 1670G configuration files has been updated to properly create an XML file.
The trigger status now displays when in Enhanced Trigger Mode.
Netlist import provides better detection and handling of missing bits from a bus.
All Advanced Logical Design configurations have been updated to support the XML configuration format.
The N4220B and B4233B FPGA firmware has been updated to properly de-skew lanes.
Version 03.00 of the logic analyzer application includes the following.
16720A Pattern Generator support: Support includes a 167xx pattern generator ASCII translator and a Pattern Generator Binary (PGB) translator.
Eye Scan with Threshold and Sample Position Setup: Ensures accurate data capture and allows you to identify problem signals quickly by displaying eye diagrams simultaneously across all channels. In all types of eye finder runs, the number of transitions is indicated by brightness. There are three types of eye finder runs available:
Auto Sample Position Setup — Performs a scan that automatically adjusts the sample position.
Auto Threshold and Sample Position Setup — Performs a scan that shows the voltage swing and automatically adjusts the threshold and sample position.
Eye Scan with Threshold and Sample Position Setup — Performs a full voltage and time scan that detects and maps transitions. This mode displays eye diagrams and automatically adjusts the threshold and sample position.
Advanced Customization Environment: Extends the data analysis and visualization capabilities of the logic analyzer by seamlessly integrating Visual Basic for Applications (VBA) into the logic analyzer application. B4606A provides the development and runtime package. B4607A provides the runtime package only. Customization possibilities include:
Data Analysis: Easily execute repeated analysis functions, like computing statistics on data captured by the logic analyzer, by creating macros/dialogs for repeated tasks.
Data Visualization: Quickly gain insight into system operation and identify areas for optimization by graphing captured data using the VbaView window. You can plot data using line graphs, XY scattergrams, horizontal and vertical bar charts, stacked horizontal and vertical bar charts, pie charts.
Instrument Control, Measurement Automation: Rapidly run through test suites by modifying the trigger for the next run based on analysis of the captured data.
Link to external PC applications: Automatically launch and export data to other COM enabled PC applications for post-processing and analysis.
B4608A ASCII Remote Programming Interface support: This package provides backward compatibility with 16700-series logic analyzers by converting 16700 ASCII RPI commands into 16900 COM commands. Requires the Advanced Customization Environment (either the B4606A Development and Runtime package or the B4607A Runtime package).
B4655A FPGA dynamic probe feature additions:
Support for Xilinx Virtex 4 devices.
Ability to create and change the names of devices, cores, and banks.
Preservation of signal properties when changing between banks. Properties include symbols, waveform size and color, etc.
Retains addition, deletion or change of a signal within a bank.
Ability to power ATC2 core off from logic analyzer.
Usability improvements for single session, multi-core support. Also shows which configuration file is loaded for each FPGA.
Includes Xilinx ChipScope Pro 6.3i JTAG drivers, improving compatibility for scan-chains with non-Xilinx devices.
Extended oscilloscope support for the E5850A Time Correlation Fixture: Time-correlate logic analyzer traces to analog traces from the following Agilent oscilloscopes:
'Go Online' modifications: Added access to the 'Password Protect the Local System from Remote Connections' utility and separated the system connection information for local and remote systems in the 'Select System to Use' dialog.
Compare modifications:
'Compare Until' button: Added a 'Compare Until' button in the main Compare Window. Selecting the button brings up the Compare Properties dialog defaulted to the Difference Properties tab.
Disable compare for a given run: A 'Disable' selection has been added to the pulldown of the Compare Window icon in the Overview tab. When selected, the Compare Window icon will remain in the Overview, the Reference Buffer will be retained, and the current acquisition will not be kept (only in the compare window). If you want to save the current trace data for compare, save it to a configuration file prior to disabling Compare. When compare is re-enabled it will use the reference trace and the current trace.
Stop key activity: While running Compare repetitively, the Stop button on the front panel will stop the comparison and the repetitive run progression window even when the progression window has focus.
Run while application is iconified: Whether interfacing to the logic analyzer through the GUI or via COM, the logic analyzer will continue to run and take data even when the application is iconified.
Symbol Name Search: A 'Symbol Name to find' field has been added to the Select Symbol Dialog. Typing characters in the field lets you quickly search for a particular symbol name. The field is active when the Name column is selected.
Windows XP Service Pack 2: Use of Windows XP Service Pack 2 requires logic analyzer application software version 3.00 or higher. Service Pack 2 focuses mainly on security and provides better protection against viruses, hackers, and worms. It includes the most up-to-date drivers, tools, security updates, and patches. It includes Windows Firewall, Pop-up Blocker for Internet Explorer, and the new Windows Security Center.
All 1680- and 16900-series logic analyzers manufactured after the release of version 3.00 of the Agilent Logic Analyzer application software will have Windows XP Service Pack 2 automatically installed.
To update an existing Windows XP 1680- or 16900-series logic analyzer:
Apply critical updates from Microsoft (retains data and license files).
Or, use September 15, 2004 or later Agilent logic analyzer recovery CDs to rebuild the logic analyzer OS (requires backing up data and license files and installation of latest logic analyzer application software)
N4220A/B PCI Express Packet Analysis Probe support: Provides the ability to decode PCI Express bus data when used in conjunction with the Packet Decoder tool. Custom packet events from traces captured on a 16700 series frame can be imported as XML files. To do this requires 16700-series application software version A.02.90.0000.
FSI-60097 and FSI-60105 FB-DIMM (fully buffered DIMM) probe support: Provides protocol decode of the 4.8 Gb/s transmit and receive channels running between the memory controller and the advanced memory buffer (AMB).
N4219B Serial ATA Protocol Analysis Probe support: Provides:
Protocol decode at full speed.
Spread spectrum clocking (SSC) and out-of-band signaling (OOB)
Built-in packet recognizers that provide powerful triggering without consuming logic analyzer resources.
Time-stamped traffic for time-correlation measurements with other system buses such as a microprocessor system bus (FSB), memory interface, or PCI-Express.
Protocol decode of a bi-directional link requires 68 channels with 200 MHz or above state capture. Works with the 16900-series modular logic analysis systems, as well as the 1680/90-series standalone logic analyzers.
E8045A/B Intel Pentium 4 Analysis Probe support: Simplifies tracing of the Pentium 4 system bus by aligning data, address, and control signals with b-clk. Provides four modes of analysis: all, compacted, expanded and timing pass-through.
E8047A/B Intel Xeon Analysis Probe support: Simplifies tracing of the Xeon system bus by aligning data, address, and control signals with b-clk. Provides four modes of analysis: all, compacted, expanded and timing pass-through.
InfiniBand Probe support: Provides the ability to decode InfiniBand bus data when used in conjunction with the Packet Decoder tool. Custom packet events from traces captured on a 16700-series logic analysis system frame can be imported as XML files. To do this requires 16700-series application software version A.02.90.0000.
E9520A Motorola PowerQUICC III (MPC8540/8560) Analysis Probe support: Inverse assembler supports instruction decode on the DDR and GPCM buses.
Version 02.50 of the logic analyzer application includes these changes:
B4655A FPGA dynamic probe support (AddIn): The FPGA dynamic probe software gives you easy access to signals internal to Xilinx FPGAs and provides significant productivity improvements when debugging FPGA designs. The dynamic probe lets you view up to 64 internal probe points for every external pin dedicated to debug. It measures new groups of internal FPGA signals in seconds without design changes. It also eliminates error-prone and time-consuming tasks with automated signal/bus name importing from the FPGA design software to the logic analyzer.
N4220A/B PCI Express Packet Analysis Probe support (AddIn): Provides the ability to decode PCI Express bus data when used in conjunction with the Packet Decoder tool. Custom packet events from traces captured on a 16700-series frame can be imported as XML files. To do this requires 16700-series application software version A.02.90.
Probe control column in Overview window: A separate column has been added to the Overview window for probes. The probe column provides access to the control and/or properties dialogs for the selected probe. Probe types available with this release are the FPGA dynamic probe, the general-purpose probe set (Soft touch, Mictor, Samtec, Flying lead), and the N4220A/B PCI Express Packet Analysis Probe.
General purpose probe set (AddIn): The general purpose probe software lets you set up soft touch, Mictor, Samtec and flying lead probe definitions in order to:
Trigger Out "Feedthrough" mode (16900-series): Added Feedthrough mode to Trigger Out. Feedthrough mode is used to control the duration of the Trigger Out signal by setting and clearing a flag connected to Trigger Out.
Eye finder (1680- and 1690-series): Eye finder automatically adjusts the sampling position for all signals and buses when in state mode. It can correct for the small delay effects caused by probe cables and circuit board traces. This makes the logic analyzer’s setup/hold window smaller and lets you accurately capture data at higher clock speeds. This capability, previously available in the 16900-series, is now also available for the standalone 1680-series and the PC-hosted 1690-series logic analyzers.
Installation package for Motorola MPC8260 support properly completes installation.
Increment/decrement arrows in the time field for the "Pattern present for >t time" trigger function provide access to the full time range allowed.
Unused pods have been removed from XML configuration files for Agilent PowerPC 405, ARM, and Motorola 683xx configuration files. This allows the configuration files to load in the lowest channel count configuration possible.
Version 02.00 of the logic analyzer application includes these changes:
16900-series modular logic analysis system support:
| Agilent model number: | 16900A | 16902A | 16903A |
|---|---|---|---|
|
Number of module slots: |
6 |
6 |
3 |
|
Multiframe Pro: |
Yes |
Yes |
No |
|
Display and resolution: |
Uses external monitor. Supports up to four external monitors at up to 1600 x 1200 (with PCI video card) |
Built-in color touch screen display, 12.1 inch at 800 x 600, supports up to four external monitors at up to 1600 x 1200 (with PCI video card) |
Built-in color touch screen display, 12.1 inch at 800 x 600, supports up to four external monitors at up to 1600 x 1200 (with PCI video card) |
|
PCI expansion slots: |
2 full profile, |
2 full profile, |
1 full profile, |
16910A (102 channels) and 16911A (68 channels) logic analyzer module support:
16950A state/timing logic analyzer module support:
Split analyzer: You can split a logic analyzer into two logic analyzer modules. This is useful for analyzing buses with different clocks.
Eye finder (16900-series): Eye finder positions the logic analyzer's setup/hold window (or sampling position) so that data on high-speed buses is captured accurately, in other words, so that data is sampled when it is valid. Eye finder measures the location of the stable region boundaries for signals and buses and automatically places the logic analyzer's sampling position in the center of the stable region. Eye finder use is recommended when the device under test's data valid window is less than 2.5 ns (roughly, for clock speeds >= 200 MHz).
Symbols: You can use symbol names in place of bus/signal data values when:
Symbol names can be: variable names, procedure names, function names, source file line numbers, etc. You can enter user-defined symbol names, or you can load symbol name definitions from a program's object file or from a general-purpose ASCII format symbol file.
Supported symbol file formats are:
Source code correlation: You can display the high-level language source code associated with captured data and set up triggers based on source code locations in the new Source display window.
Dual-sample sampling clock mode: In the Dual Sample state sampling clock mode, you can save data captured using the master clock at each of two different sample times into the same sample of analyzer memory. The Dual Sample mode is often used to capture DDR memory bus activity using the common bus clock as the master clock. One sample position is used to capture write data and another is used to capture read data.
Multiframe Pro (16900A and 16902A): When you need to make time-correlated measurements with more logic analysis channels than can be installed in a single frame, you can connect multiple 16900A and 16902A logic analysis system frames together. All measurement modules in the system are displayed through a single user interface. The system auto-detects all frames connected together at power up.
Hosted Power Mode: Achieve the ultimate in performance by hosting the logic analyzer application software on your fastest multiprocessor server to remotely control the logic analyzer or do offline analysis.
Multiple monitor support: Get the most comprehensive view of your data by expanding the display across multiple monitors with extended desktop viewing.
Probe definition: This dialog lets you define buses and signals directly from a schematic or netlist without having to figure out the pin mapping for the probe.
PowerQUICC III support: Inverse assembler supports instruction decode on the DDR and GPCM buses.
Motorola MPC74xx support: Inverse assembler supports instruction decode on the 60X and MPX buses.
400 MHz Transitional Mode (1680/1690-series logic analyzers): The maximum transitional timing speed for the 1680/1690-series logic analyzers has been increased to 400 MHz.
Fast binary file format (.mfb): Saving an XML file with data creates an XML setup file with pointers to fast binary files (.mfb) containing the data. Mfb files can be quickly transferred over LAN to a PC for use with custom analysis tools.
Programming examples: Additional programming examples can be accessed by selecting Help, Help Topics (Contents Tab), COM Automation, Using COM Automation. Examples are provided for Visual Basic and LabVIEW. Additional Visual Basic examples can be found in the default installation example directory C:/Program Files/Agilent Technologies/Logic Analyzer/LA COM Automation/Visual Basic Examples.
167xx Configuration File Translator: The 167xx configuration file translator is installed along with logic analyzer application software. It is accessed from the Windows menu bar: Start, Programs, Agilent Logic Analyzer, Utilities. The utility translates the individual module acquisition setup for 1674x and 1675x measurement modules. The output of the translator is a generic XML configuration file, making the configuration portable to all acquisition hardware supported by the 16900-series logic analysis systems.
If the 167xx configuration file was saved with data, you can view the data in the Agilent Logic Analyzer application by saving the data in the fast binary format on the 16700. From the Agilent Logic Analyzer interface, select File>Import and follow the instructions in the 16700 Fast Binary Data Import Wizard.
CSV file format modifications:
When loading a configuration, updates to the trigger are delayed until trigger initialization is complete.
Configuration files (.ala) created on any previous version for the 1680/1690-series logic analyzers will load into a 1680/1690-series logic analyzer with version 02.00.
All waveform resizing completes prior to accepting additional changes. Cancel can be selected at any time to stop the current action in order to make additional changes.
The Found marker is initialized when a configuration file is loaded. If you have not performed an initial Find, selecting Find Next will occur like an initial Find.
The symbol value remains the same when the Quick Trigger box is drawn.
The clock bit can be used as a data bit. When used in this manner the data bit is appropriately initialized.
When a .ala configuration file from an analyzer with a given channel count and/or memory depth is loaded into an analyzer from the same family with a different channel count and/or memory depth, the configuration is loaded; however, some of the configuration settings may change to the closest setting available for the analyzer with the different channel count and/or memory depth. Example: the configuration file may have been saved with a maximum memory depth of 4 M. It is then loaded into an analyzer in the same family that has a maximum memory depth of 1 M. On the first run after loading the configuration, the memory setting will automatically change from 4 M to 1 M.
To view and analyze the data saved with the original configuration file, load the file into an Offline session.
Characteristic definition corrected in online help.
Time interval accuracy = +/-(sample period + channel-to-channel skew + 0.01% of time interval reading)
Version 01.40 of the logic analyzer application includes these changes:
Cross-trigger and make time-correlated measurements between the logic analyzer and an external Agilent 548XX oscilloscope: The logic analyzer now supports the E5850A time-correlation fixture. The E5850A automatically deskews the measurements, coordinates runs, and coordinates marker moves between the logic analyzer and Infiniium 548XX oscilloscope.
Reorder bits assigned to a bus: In cases where buses in the device under test are not physically probed by consecutive logic analyzer channels, you can reorder the bits assigned to buses.
Import bus/signal names from a netlist file: Quickly setup the logic analyzer configuration to match your target signal's bus and signal names by importing a netlist file. Netlist files contain information about the signals on the connectors built into the device under test. The connectors correspond to connections for the logic analyzer probes. Netlist files come from the Electronic Design Automation (EDA) tools used to design the device under test.
Remote programmatic control: The logic analyzer application now includes the COM Automation Server, enabling remote programmatic control of the logic analyzer. This software lets you write programs in Visual C++ or Visual Basic to control the logic analyzer from remote PCs on the Local Area Network (LAN).
Generic XML configuration files: You can save trigger specifications in XML format and transfer them between different logic analyzers. Also, you can use portions of generic XML configuration files with several of the COM remote programming commands to modify the logic analyzer's setup from run-to-run.
The Overview window lets you specify how captured data is post-processed and displayed: You can display the same data in multiple windows by using the Overview window (which replaces the previous Tool Overview dialog); for example, you can display the same data filtered in one Listing window and unfiltered in another Listing window.
Set delay between repetitive measurements: This feature allows you to look at captured data and allow you to stop a repetitive measurement before the next run occurs.
Locked scrolling of display windows: You can now lock the scrolling on display windows (for example Waveform, Listing, or Compare) so that when one window is scrolled, all specified locked windows are scrolled as well. You can find the Lock property with other windows property settings.
Statistics and Run until... capability for Interval markers: You can now show statistics, stop a repetitive measurement or send an email message on particular statistic values for interval markers. Interval markers are used to measure the time interval or the number of samples between two specified points in the data. If statistics are shown, the low, high, and average interval measurements are provided in the marker measurements display bar.
Bus/signal names and number base added to export for CSV files: When exporting data to comma-separated value (CSV) files, you can now choose to export data from selected buses/signals in addition to pod information. You can also select the number base of the data that is exported. CSV files can be imported into spreadsheet, database or other data analysis programs.
Define trigger event evaluation by grouping events using parenthesis: When specifying advanced triggers with multiple events in an event list, you can specify the evaluation order by grouping the events.
Quick pick for bus/signal names: This feature allows you to quickly select bus/signal names from recently used names. This feature has been added to the Filter/Colorize tool properties dialog and to the advanced trigger setup dialog.
New location for specifying Run until... for Compare measurements: Run until is now specified from the Difference Properties tab in the Compare window's Properties window.
A 169x firmware update is available for the case when the 169x will not operate when it is turned on after being connected to a PC that is already running. The necessary software to update the 169x firmware can be obtained at ftp.cos.agilent.com/dist/169x.
Fake data generated for Offline mode now corresponds to the memory depth, trigger position, and sampling period controls in the sampling tab of the setup menu.
The Waveform control area now responds to quick access key combinations.
The logic analyzer's ARM in trigger has been modified to be edge sensitive instead of level sensitive.
When signals in a bus grouping are all high or all low, the Waveform display now draws a line at the top or line at the bottom respectively instead of a bus 'box'.
The Markers center about dialog has been changed to use two combo boxes for marker selection rather than presenting all the possible marker pairs.
Imported 16700-series Fast Binary Out (FBO) data can now be saved in a CSV file.
All or part of the captured data listing can be exported to a CSV file.
The 167xG configuration file translator now creates a 1680/169x configuration file in XML format. The .txt format is no longer supported.
When importing 16700-series Fast Binary Out (FBO) data that contains data from multiple sources, you may have buses or signals with the same bus/signal name. You can distinguish buses/signals of the same name by selecting 'Show Bus/Signal Folder' in the Edit>Options... dialog. This option provides the full path for the name so you can determine the original source.
When doing a Compare of 16700-series FBO, the logic analyzer application looks for the beginning and end of the data. Taking 16700-series FBO data at the compare tool allows you to import the Diff Flag data. Taking the 16700-series FBO data at the instrument allows you to specify a single data set as your golden reference trace.
The logic analyzer application supports paged and non-paged data together when importing 16700-series FBO data. The application previously handled paged or non-paged data separately. The application will skip string data in FBO files.
The Odd/Even pod selection for half-channel mode presents the correct data for the chosen half of the pod pair.
Edge triggering for the simple trigger mode now correctly aligns with the trigger position on every run.
Version 01.20.0300 of the logic analyzer application includes these changes:
Version 01.20.0200 of the logic analyzer application includes these changes:
Version 01.20.0100 of the logic analyzer application includes these changes:
Version 01.20 of the logic analyzer application includes these changes:
16700-series Offline Analysis: Import and view data captured on Agilent 16700-series logic analyzers. Save 16700-series data with the Fast Binary format of the File Out tool. Transfer the 16700-series Fast Binary file(s) to a PC running the logic analyzer application. Use the `167xx Fast Binary Files' selection in the application's File>Import dialog to import the data.
Windows XP compatibility: The Agilent logic analyzer application runs on PCs with Windows NT, Windows 2000 Professional, or Windows XP. The application supports direct operation of 1690-series PC-Hosted logic analyzers as well as offline viewing and analysis of 16700-series, 1680-series and 1690-series data.
Trigger on multiple edges/glitches in the timing (asynchronous) sampling mode. Select Edge When specifying a bus trigger evaluation condition in the Advanced Trigger dialog. The Edge Spec... dialog lets users specify edges/glitches by individual signal. Specifying an edge or glitch on more than one channel logically ORs the edges together.
Compare lets you perform a compare of captured data sets. From the menu bar, select Window>New Compare... to bring up a Compare viewer. You can copy data from any or all of the labels to establish a 'golden' reference trace. Features include the ability to stop a repetitive run after a specified number of differences and email after a specified number of differences. You can specify the range of data to compare. Also, when there are differences in the number of samples captured before the trigger, or when you are comparing a range of samples, you can offset the reference data so that the samples being compared are properly aligned.
Email on trigger. When defining the trigger action in a trigger sequence, you now have 'Trigger, send e-mail, and fill memory' as a choice.
Save/load user-defined symbols to/from XML format logic analyzer configuration files. This means you can use text processing tools to re-format symbol information from software development tools, insert them into an XML format configuration file, and load them into the Agilent Logic Analyzer application.
The Agilent Logic Analyzer install CD has an Analysis AddIn Wizard that helps you develop your own inverse assemblers or analysis tools. The Analysis AddIn Wizard works with Microsoft Visual C++ Studio.
To install the Analysis AddIn Wizard:
Support for HTML tags has been added for inverse assembler and analysis tool usage. Includes bold, underline, italic, and color within strings.
Capability to search for a string or filter on a string with Inverse Assembly data.
You can zoom by either drawing a box and selecting 'Zoom In' from the pop up OR you can Autozoom in Waveform by holding down the CTRL key while you draw a box around the area you want to zoom in on.
Chart is easier to access. Simply right click on a label in Waveform and select Bus/Chart... in the pop up dialog. You can now view Chart data as individual dots or as a line that connects the dots.
The .xml file size limit can be set under Edit>Options dialog. Adjust the file size limit using the Generic Config Save Limit field.
Establish ascending/descending label sorting in the bus/signal section of the Setup dialog. Once established, dialogs used to insert labels maintain the same sorting order.
Foreground color (text) has been added to the Marker Properties dialog. The Background color designates the marker color.
The Filter dialog defaults to no active filters. Use the `Click here to insert new filter' field to specify the filter condition.
Use the CTRL+ to resize columns to the width of the widest entry in the column. Use the '+' from the keypad.
Searching is now based on 'forward/backward' rather than 'negative/positive'.
License files for licensed add-in products and the logic analyzer application need to be on the same drive for the licensed add-in products to work.
The listing and waveform print options now have fields to input the left, top, bottom, and right margin width in inches. Printing a screen, scrolling and printing the next screen now works properly.
Version 01.10 of the logic analyzer software includes these changes:
Agilent's Windows-based logic analyzers are designed to match your work style, application and budget.
The 16900-series logic analysis system mainframes:
| Model: | 16900A | 16902A | 16903A |
|---|---|---|---|
|
Number of module slots: |
6 |
6 |
3 |
|
Multiframe Pro: |
Yes |
Yes |
No |
Logic analyzer modules supported in the 16900-series logic analysis system mainframes:
| Model: | 16950A | 16910/11A | 16753/54/55/56A | 16750/51/52A/B | 16740/41/42A |
|---|---|---|---|---|---|
| Channels per card (up to 5 cards)*: | 68 | 16910A: 102 16911A: 68 |
68 | 68 | 68 |
| Memory depth*: | Option 256: 256 K Option 001: 1 M Option 004: 4 M Option 016: 16 M Option 032: 32 M Option 064: 64 M |
Option 256: 256 K Option 001: 1 M Option 004: 4 M Option 016: 16 M Option 032: 32 M |
16753A: 1 M 16754A: 4 M 16755A: 16 M 16756A: 64 M |
16750A/B: 4 M 16751A/B: 16 M 16752A/B: 32 M |
16740A: 1 M 16741A: 4 M 16742A: 16 M |
| Timing zoom sample rate: | 4 Ghz | 4 GHz | 4 GHz | 2 GHz, 1 GHz, 500 MHz, 250 MHz | 2 GHz, 1 GHz, 500 MHz, 250 MHz |
| Timing zoom memory depth: | 64 K | 64 K | 64 K | 16 K | 16 K |
| Timing sample rate (full channels): | 600 Mhz | 500 MHz | 600 MHz | 400 MHz | 400 MHz |
| High-speed timing sample rate (half channels, double memory): | 1200 Mhz | 1000 MHz | 1200 MHz | 800 MHz | 800 MHz |
| State clock rate, data rate: | 300 MHz, 300 Mb/s |
250 MHz, 250 Mb/s |
300 MHz, 300 Mb/s |
200 MHz, 200 Mb/s |
200 MHz, 200 Mb/s |
| High-speed state clock rate, data rate: | 600 MHz, 800 Mb/s |
Option 500: 450 MHz, 500 Mb/s |
600 MHz, 800 Mb/s |
400 MHz, 400 Mb/s |
N/A |
|
*
In the state sampling mode, choosing the maximum
acquisition memory depth requires one pod pair (34 channels)
to be reserved for time tag storage. In this case, setting
the memory depth to half of the maximum (or less) will
return the pod pair. In the high-speed state sampling mode, one pod pair (34 channels) is reserved for time tag storage. In the transitional timing sampling mode: - When the smallest sampling period is selected, one pod pair (34 channels) is reserved for time tag storage. - When sampling periods other than the smallest are selected, choosing the maximum acquisition memory depth requires one pod pair to be reserved for time tag storage. In this case, setting the memory depth to half of the maximum (or less) will return the pods. |
|||||
Eight 1680-series benchtop logic analyzer models and eight 1690-series PC-hosted logic analyzer models offer a variety of channel counts and memory depths. Each provides the same performance, core features and functionality in a small footprint that saves valuable workspace.
| Model: | 1680A/AD, 1690A/AD | 1681A/AD, 1691A/AD | 1682A/AD, 1692A/AD | 1683A/AD, 1693A/AD |
|---|---|---|---|---|
| Channels*: | 136 | 102 | 68 | 34 |
| Memory depth*: | 1680A: 512 K 1690A: 512 K 1680AD: 2 M 1690AD: 2 M |
1681A: 512 K 1691A: 512 K 1681AD: 2 M 1691AD: 2 M |
1682A: 512 K 1692A: 512 K 1682AD: 2 M 1692AD: 2 M |
1683A: 512 K 1693A: 512 K 1683AD: 2 M 1693AD: 2 M |
| Timing sample rate (full channels): | 400 Mhz | 400 MHz | 400 MHz | 400 MHz |
| High-speed timing sample rate (half channels, double memory): | 800 MHz | 800 MHz | 800 MHz | 800 MHz |
| State clock rate, data rate: | 200 MHz, 200 Mb/s |
200 MHz, 200 Mb/s |
200 MHz, 200 Mb/s |
200 MHz, 200 Mb/s |
|
*
In the state sampling mode, choosing the maximum
acquisition memory depth requires one pod pair (34 channels)
to be reserved for time tag storage. In this case, setting
the memory depth to half of the maximum (or less) will
return the pod pair. In the transitional timing sampling mode: - When the smallest sampling period is selected, one pod pair (34 channels) is reserved for time tag storage. - When sampling periods other than the smallest are selected, choosing the maximum acquisition memory depth requires one pod pair to be reserved for time tag storage. In this case, setting the memory depth to half of the maximum (or less) will return the pods. |
||||
For the 16900-series logic analysis systems and the 1680-series logic analyzers, the logic analyzer software is installed at the factory. Product install and recovery CDs are shipped with the product. Add-in products can be installed from the install CD.
For the 1690-series logic analyzers, the logic analyzer software and one or more add-in products can be installed from the product install CD.
The default installation location for the logic analyzer and all add-in products is:
C:\Program Files\Agilent Technologies\Logic Analyzer
The default location for user data files is:
C:\Documents and Settings\<USERNAME>\Application Data\Agilent Technologies\Logic Analyzer
During installation, information is written to these areas of the Windows Registry:
HKEY_LOCAL_MACHINE/SOFTWARE/Agilent Technologies/Logic Analyzer
HKEY_LOCAL_MACHINE/CLSID/{Various GUIDs}
During installation, the ".ala" suffix is associated with
the Agilent logic analyzer as a file type.
Double-clicking on a configuration file with the ".ala"
suffix will start up the logic analyzer and load that
configuration.
|
NOTE: |
The 16900-series logic analysis systems and the 1680-series logic analyzers runs the English-only version of Microsoft Windows XP Professional. Software applications requiring font support for languages other than English may not work properly. |
In the logic analyzer "Help>About" dialog there is a page of URLs pointing to various sites within Agilent Technologies. The URLs are duplicated here:
Agilent Technologies: www.agilent.com
Logic Analyzers: http://www.agilent.com/find/logic
Logic Analyzer Software Download: http://www.agilent.com/find/la-sw-download
Software on CD: http://software.cos.agilent.com/LogicAnalyzerSW
Email Updates: http://www.agilent.com/find/emailupdates
Contact Us: http://www.agilent.com/find/contactus
Also, the online help system is available within the product.
The Agilent logic analyzer supports add-in products, which provide additional functionality such as inverse assembly. Currently, add-in products include:
You can activate your add-in products using this process:
<YourInstallLocation>\License
For a standard installation, this would be:
C:\Program Files\Agilent Technologies\Logic Analyzer\License
Once the license file is installed, selecting the add-in via Tool>New in the logic analyzer will load the add-in.
Here is a sample license file:
FEATURE PowerQUICC_Inverse_Assembler agilent 1.0 permanent uncounted \
HOSTID=DISK_SERIAL_NUM=3a5a7c1c SIGN=43F2F9A6DC40
© Agilent Technologies, Inc. 2004-2007