Here’s the page we think you wanted. See search results instead:

 

Contact an Expert

Technical Support

U7233B DDR1 Compliance Test Application with LPDDR and mobile-DDR Support for Infiniium Scopes

Product Status: Currently Orderable | Currently Supported

View Product Details

Current Firmware/Software

Version: 01.54
Release Date: 2017-04-21

Refine the List

By Type of Content

1-15 of 15

Sort:
Remote Programmer's Reference, U7233A/B DDR1 Compliance Test Application
Describes the test names and IDs and the configuration variable names used when writing programs to remotely control the Keysight U7233A/B DDR1 compliance test application software.

Programming and Syntax Guide 2017-04-19

PDF PDF 261 KB
Compliance Testing Notes, U7233A/B DDR1 Compliance Test Application
Describes how tests are implemented in the Keysight U7233A/B DDR1 compliance test application software.

User Manual 2017-04-01

PDF PDF 5.02 MB
Online Help, U7233A/B DDR1 Compliance Test Application
Describes how to use the Keysight U7233A/B DDR1 compliance test application software.

Help File 2017-04-01

CHM CHM 12.12 MB
U7233A DDR1 Compliance Test Application
The Keysight Technologies U7233A DDR1 compliance test application provides a fast and easy way to test, debug and characterize your DDR1 designs.

Data Sheet 2016-04-20

N5413B and N5413C DDR2 and LPDDR2 Compliance Test Application – Data Sheet
The N5413B DDR2 and LPDDR2 compliance test application provides a fast and easy way to test, debug and characterize your DDR2 and LPDDR2 designs.

Data Sheet 2016-04-15

U7231A DDR3 Compliance Test Application for Infiniium Series Oscilloscopes - Data Sheet
The U7231A DDR3 compliance test application provides a fast and easy way to test, debug and characterize your DDR3 designs.

Data Sheet 2014-08-01

DDR Memory Design and Test – A Better Way
Keysight offers the complete solutions for all areas of DDR design, meeting your needs for electrical physical layer, protocol layer, and functional test.

Brochure 2012-12-19

PDF PDF 5.17 MB
DDR Memory Design and Test Overview
Brief overview of Keysight solutions for DDR design and test.

Brochure 2012-12-19

PDF PDF 1.14 MB
Validating the Physical and Protocol Layers in DDR Memory Interfaces

Article 2009-01-06

Eye-Diagram Analysis Speeds DDR SDRAM Validation

Article 2009-01-06

A Time-Saving Method for Analyzing Signal Integrity in DDR Memory Buses
This application note covers new tools and measurement techniques for characterizing and validating signal integrity of DDR (double data rate synchronous dynamic random access memory) signals.

Application Note 2008-09-10

Simplify DDR Validation with SI Methods

Article 2008-01-06

DDR 1, 2 and 3 solutions Video
Includes probing methods, read/write separation technique and automated JEDEC compliance measurements with Infiniium Series oscilloscopes.

Demo 2007-12-27

WMF WMF 52.75 KB
Improve Your Time-to-Insight:Debugging Intermittent Memory Failures in DDR and DDR2 Systems
Application Note 1575

Application Note 2006-04-14

Designing and Validating High-Speed Memory Buses (AN 1382-2)
DDR SDRAM (double data rate synchronous dynamic random access memory) is quickly becoming an accepted technology in the PC (personal computer) industry. Its low cost, high performance, and increasingly wide availability make it very desirable for PC memory buses and embedded designs such as high...

Application Note 2001-12-20