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E9524A MicroBlaze Trace Toolset

Data Sheets

Easily Trace Microblaze Software Execution with Keysight Microblaze Trace Core and Inverse Assembler

Keysight Technologies, Inc. and Xilinx have developed a logic analysis trace solution for Xilinx’s MicroBlaze embedded processor that overcomes the traditional difficulties of tracing software execution using a logic analyzer. Combining the capabilities of a MicroBlaze inverse assembler with a specialized trace core simplifies measurement setup and reduces the number of pins required. In addition, the trace core overcomes the lack of visibility you encounter when you employ cache and pipelining and unlocks the power of the logic analyzer to make accurate measurements. You get easy access to the insight you need to increase the quality of your design and ensure its timely completion. 

MicroBlaze Inverse Assembly

For PC board layout, you enable the inverse assembler by first choosing the level of visibility you need and then routing the corresponding MicroBlaze signals to pins. The MicroBlaze inverse assembler allows a choice of instruction-side and/or data-side decoding, and can accommodate variations of bus widths and different combinations of the signals to allow maximum flexibility. For example, instruction-side decoding would require routing at least the MicroBlaze program counter signals (PC_Ex) and the valid cycle signal (Valid_Instr) to pins. Routing these signals to a specified layout allows for fast connection to a logic analyzer via mictor, Samtec, or soft touch probing. Or, you can connect the logic analyzer to these signals with individual flying leads attached to a berg strip or header. 

Because FPGAs with MicroBlaze cores are reprogrammable, they can be traced late in the development cycle. As long as you have reserved a sufficient number of pins for debug, you can route required MicroBlaze signals to a specified pinout without PC board changes. 

The Keysight inverse assembler for MicroBlaze reconstructs program flow by capturing the address of each executed instruction and looking up the associated opcode in the OMF (object module format) file. It then decodes the opcode into a MicroBlaze instruc­tion, as shown in Figure 1.  

Keysight logic analyzers also come standard with a source correlation window so you can setup a measurement at the assembly or source level.

Debug Using Fewer Pins

Pins available for debug are often scarce, so the inverse assembler includes a capability that reduces the number of required pins. Although the MicroBlaze architecture has 32 PC_Ex signals, the number of external signals needed for capturing a logic analysis trace is typically significantly less than 32. 

This reduction is accomplished using two different techniques. First, any upper address bits that are static do not need to be traced, so one pin can be eliminated for each static upper address bit in the program counter. You can specify this information via the logic analysis user interface. Second, the lower two address bits also do not need to be traced, since all instructions start on 4-byte boundaries. Using these techniques, tracing software execution of a 1-Mbyte program requires only 18 pins (plus 1 clock pin and 1 control pin). Keysight’s MicroBlaze trace core provides further pin reduction by using a 2:1 time-domain-multiplexing capability in conjunction with the Keysight logic analyzer. This enables an additional 50% reduction in pins required for trace.

Correlate Assembly Mnemonics with High-Level Source Code, Even with Cache Enabled

MicroBlaze execution can be tracked deterministically, even when cache is enabled, since captured signals are routed from the execution stage of the MicroBlaze pipeline. This also makes the trace impervious to unused prefetches.  

Keysight logic analyzers come standard with a source cor-relation window. By reading a symbol file (.elf format), the logic analyzer can associate captured addresses with the high-level software mapped to that address. When you step through assembly instruc­tions, the equivalent line in the source code for this instruction is also highlighted. Or, step through high-level source code while the logic analyzer simultaneously displays the associated instruction mnemonics in the lower window. Right click in the source code to quickly set up the logic analysis trigger (trace specification) for the next acquisition, as shown in Figure 2.

MicroBlaze Trace Core

The MicroBlaze trace core (MTC) reduces setup time and the number of pins required to trace a MicroBlaze processor instance. The MTC core, co-developed by Keysight and Xilinx, works exclusively with the Xilinx Platform Studio, which is included with the Xilinx embedded development kit (EDK) design flow. It allows you to graphically add an MTC core to your design. Core parameters include data values, status signals, pin compres­sion using time division multiplexing, pin location, and I/O standard.

The MTC core works together with Keysight’s FPGA dynamic probe logic analyzer soft­ware to provide four key benefits:

1. The MTC core connects required MicroBlaze signals to FPGA pins (pre-synthesis).

2. The core can be configured to reduce the number of pins required by a factor of two. Two MicroBlaze signals are time-division-multiplexed onto a single pin with data valid on the rising edge of the clock for signal one and data valid on the falling edge of the clock for signal two. A demux clocking mode in the logic analyzer decompresses the information and splits it into two separate logic analysis channels.

3. The MTC core includes auto pin-mapping that reduces initial setup time from hours seconds and eliminates manual errors that can happen during the PC board layout. Tracing MicroBlaze can be done late in product development, as the MTC core eliminates the need to ayout a PC board with a specific MicroBlaze signal pattern (see Figure 4).

4. Via JTAG, the logic analyzer sends an auto setup message to the MTC core. The core outputs a training pattern on a specific MTC pin. The logic analyzer looks for this training pattern across its channels and discovers which channel is connected to the MTC pin. By repeating this process for each MTC output pin, the logic analyzer learns how each MTC core input is routed through the core to pins and through connectors and/or probes to the logic analyzer. 

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