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B4656A FPGA Dynamic Probe for Altera

Data Sheets

The Challenge

You rely on the insight a logic analyzer provides to understand the behavior of your FPGA in the context of the surrounding system. Design engineers typically take advantage of the programmability of the FPGA to route internal nodes to a small number of physical pins that a logic analyzer can measure. While this approach is very useful, it has significant limitations.

  • Since pins on the FPGA are typically an expensive resource, there are a relatively small number available for debug. This limits internal visibility (i.e. one pin is required for each internal signal to be probed).
  • When you need to access different internal signals, you must change your design to route these signals to the available pins. This can be time consuming and can affect the timing of your FPGA design.
  • Finally, the process required to map the signal names from your FPGA design to the logic analyzer setup is manual and tedious. When new signals are routed out, you need to manually update these signal names on the logic analyzer, which takes additional time and is a potential source of confusing errors.

Debug Your FPGAs Faster and More Effectively with a Logic Analyzer

FPGA dynamic probe lets you:

View internal activity – With a logic analyzer, you are normally limited to measuring signals at the periphery of the FPGA. With the FPGA dynamic probe, you can now access signals internal to the FPGA. You can measure up to 256 internal signals for each external pin dedicated to debug, unlocking visibility into your design that you never had before.

Make multiple measurements in seconds – Moving probe points internal to an FPGA used to be time consuming. Now, in less than a second, you can easily measure different sets of internal signals without design changes. FPGA timing stays constant when you select new sets of internal signals for probing.

Leverage the work you did in your design environment – The FPGA dynamic probe maps internal signal names from your FPGA design tool to your Keysight Technologies, Inc. logic analyzer. Eliminate unintentional mistakes and save hours of time with this automatic setup of signal and bus names on your logic analyzer.

Design step 1: Configure the logic analyzer interface file and core parameters

You need to create a logic analyzer interface file with the logic ana­lyzer interface in Quartus II. This file defines the interface that builds a connection between the internal FPGA signals and the logic analyzer. You can then configure the core parameters, which include number of pins, number of signal banks, the type of measurement (state or tim­ing), clock and the power-up state.

Design step 2: Map the logic analyzer interface core outputs to available I/O pins

Use Pin Planner in Quartus II to assign physical pin locations for the logic analyzer interface core.

Design step 3: Assign logic analyzer interface bank parameters

Assign internal signals to each bank in the logic analyzer interface after you have specified the number of banks to use in the core parameters. Find the signals you want to acquire with the Node Finder and assign them to the banks.

With the logic analyzer interface core fully configured and instantiated into your FPGA design, you’re ready to compile your design to create the device programming file (.sof). Then, to make measurements you’ll move to the Keysight logic analyzer software.

Activate FPGA dynamic probe for Altera

The FPGA dynamic probe icon allows you to control the logic analyzer in­terface and set up the logic analyzer for the desired measurements.

Measurement setup step 1: Establish a connection between the logic analyzer and the logic analyzer interface

The FPGA dynamic probe application establishes a connection between the logic analyzer and the FPGA via a JTAG cable. It also determines what devices are on the JTAG scan chain and lets you pick the one with which you wish to communicate.

Measurement setup step 2: Configure the device and import signal names

If needed, you can configure the device with the SRAM object file (.sof) that includes the logic analyzer interface file. The FPGA dynamic probe application reads a .lai file produced by Quartus II. The names of signals you measure will now au­tomatically appear in the label names on your Keysight logic analyzer.

Measurement setup step 3: Map FPGA pins

Select your probe type and easily provide the information needed for the logic analyzer to automati­cally track names of signals routed through the logic analyzer interface file.

Setup complete: Make measurements

Quickly change which signal bank is routed to the logic analyzer. A single mouse click tells the logic analyzer interface core to switch to the newly specified signal bank without any impact to the timing of your design. To make measurements throughout your FPGA, change signal banks as often as needed. With each new selection of a signal bank, FPGA Dynamic Probe updates new signal names from your design to the logic analyzer. User-definable signal bank names make it straight forward to select a part of your design to measure.

Correlate internal FPGA activity with external measurements

View internal FPGA activity and time-correlate internal FPGA measurements with external events in the surrounding system. FPGA Dynamic Probe unlocks the power of the logic analyzer for system-level debug with FPGAs.

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