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FSI-60112 Packet Analysis Probe for PCI Express®

Data Sheets

For use with Keysight 16800 Series Portable Logic Analyzers

Introduction

The Keysight Technologies, Inc. FSI-60112 PCI Express® packet analysis probe provides a mechanical, electrical and software interface between your PCI Express bus and an Keysight logic analyzer. The probe provides quick and reliable connections to your system under test and has internal termination networks that minimize the effects of loading and reflections on your PCI Express bus during probing. The protocol decode software decodes and displays incoming data on your logic analyzer to make it easy for you to debug your design problems.

Features

  • Non-intrusive probing of PCI Express slots and chip-to-chip links in embedded system using unique soft touch connectorless probing technology
  • Configurations for a variety of link widths: x4, x2, x1
  • Support for PCI Express at full frequency (2.5+ GT/s)
  • Logic analysis triggering and decoding of PCI Express buses at the packet level with Packet Viewer and Transaction Viewer software
  • Decode for pre-defined and user-defined packet setups
  • Support for all PCI Express modes: squelch, link training, TLP, DLLP, 10b/8b, spread spectrum clock, and scrambled data
  • Designed for use with Keysight 16800 Series logic analyzer

Complete System

Use a 16800 Series portable logic analyzer with the FSI-60112 analysis probe in your development lab for design and functional validation of PCI Express devices, add-in cards, system and chip-to-chip architectures. The analysis probe provides low-intrusion probing of the bus, PCI Express packet analysis and packet triggering to help you pinpoint your problem areas quickly. The FSI-60112 supports data scrambling, spread-spectrum clocking and flexible lane widths so you can make sure your design is consistent with PCI Express standards. A variety of probing options make it easy for you to connect to your device.

Probe Connections

Three types of probe connections are available for the FSI-60112 so you can connect the probe with chip-to-chip, chip-to-slot and slot-to-slot PCI Express architectures. When you are doing point-to-point analysis between chips, it is important to physically probe the traces between them. The midbus probes with soft touch connectorless probing technology overcomes this challenge with the lowest impedance loading in the industry. For designs with a card edge slot, interposing probe solutions are available, and where there is no card edge slot or midbus footprint, there is a flying lead set for reliable data capture at full bus speed.

FSI-60112 analysis probe

The FSI-60112 is capable of probing at a serial data rate of 2.5 Gb/s – it’s the speed of standard PCI Express bus so you can be confident your bus works at PCI Express speeds. The probe monitors two directions of x1, x2 and x4 links and recognizes up to 24 bytes of each packet header so you can accurately capture the packet of interest. The probe is designed to handle a single, unidirectional link, or a bidirectional link and each may have a different reference clock.

Key features include:

  • Spread-spectrum clocking
  • Supports for ordered sets, TLP, DLLP and electrical idle
  • Fast training sequence (without extension bit) synchronization in 14 to 16 FTS
  • Jitter specification (valid data eye) – 140 ps (0.65 unit interval)

Protocol Decode Software

The analysis probe, which includes protocol decode software for 16800 Series logic analyzers, acquires serial data, converts it to parallel form, recognizes and filters packets, and clocks the information into the analyzer. Data sent to the logic analyzer includes:

  • Captured data (8 or 10 bit representation)
  • Packet type and state information
  • Packet recognizers and error indicators

This data is processed by the protocol decoder for display of packets, transactions and errors. You have the choice of viewing the packet decode data with either the Transaction Viewer tool or the Packet Viewer tool. Although the probe hardware has the ability to filter and trigger, the software interface provides bits arranged to support the use of logic-analyzer-based trigger functions, even on packet-based data. The decoder detects packet types and checks packet delimiters (minimal protocol checking).

Packet Viewer software

Packet Viewer software is a powerful tool for easy analysis of protocol traffic. Packet viewer provides bidirectional information in a single display. Packet viewer allows packet-to-packet comparisons and detailed information on each lane, header format and payload.

Transaction Viewer software

Transaction Viewer software runs on the logic analyzer to graphically display bus transactions. Start in high-level summary view to quickly scan transactions. Then use the drill-down feature to expose lower-level details of transactions or interest.

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