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When programmatically controlling the ENA and utilizing an ECAL, I do not observe the ESR bit 0 being set from 0 to 1 at the completion of the Ecal...

(SUPPORTED MODELS IN BOLD: E5071C E5070B/71B E5070A/71A E5061A/62A)

As of ENA firmware release version 6.50, the ECAL process under remote control holds off ALL subsequent programming commands until the completion of the ECAL calibration process. Based on this implementation, you can not utilize the '*ESR?' query in a loop and wait for a bit change from 0 to 1. The bit is held as a zero value until the Ecal is complete thus querying this bit in loop is not functional. The '*ESR?' will hold-off until the Ecal is complete and then return a "1".

To overcome this issue, the optimum solution is to mask the appropriate *SRE and *ESE bits combined with the use of the *OPC and then wait for a GPIB SRQ interrupt based on ECAL complete. This process is not detailed in this document, please see the related FAQ linked below for more information. While the SRQ method is optimum, it is not the easiest process to implement. The recommendations below trade-off the flexibility and optimization of an SRQ approach for ease of programming.

Rather than use an SRQ, the programmer may use an operation complete query, '*OPC?', and hold-off for the return value of a 1 in the output buffer. Another option is to query the ESR bytes via the '*ESR?' command realizing that a 1 will be returned in bit position 0 AT THE COMPLETION of the ECAL. Due to the fact that some ECAL processes with narrow IF bandwidths, multiple channels, and possible multiple ports, could require extensive delays to complete, it may be necessary to significantly increase your default timeout period. Default timeout periods are typically 2 to 5 seconds, which is often inadequate to complete a calibration. Time-out settings, which are too short, will typically result in an i/o time-out error. The SRQ process does not rely on return value and therefor is exempt from the need to adjust the time-out period.

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