SECO Reduces DDR4 Board Failures to Zero

Double Data Rate 4 (DDR4) has surpassed DDR3 as the next generation of Synchronous Dynamic Random-Access Memory (SDRAM) technology. Offering higher bandwidth, increased speeds, and improved power efficiency, DDR4 is the preferred standard of today’s engineers. DDR4 is used in high-speed computing and data center networking. LPDDR4 (Low-Power DDR4) is used in consumer electronics, autonomous vehicles, and entertainment.

As the speed of DDR technology increases, design error margins decrease, and signal integrity becomes more challenging to maintain. These challenges slow production and create product reliability issues. Signal integrity engineers must also address similar issues like crosstalk, jitter, and electromagnetic compatibility (EMC). To ensure reliable and accurate designs, they now require new tools and processes.

This is exactly the challenge facing designers at SECO, an Italian industrial group that designs and produces in-house embedded systems and IoT solutions. Their solutions range from a single microcomputer to integrated and “ready-to-use” systems. SECO manages the entire production cycle in-house, from development and design to manufacturing and mass distribution.

While working to ensure reliable operation of their designs, SECO designers faced shrinking timing and voltage margins, as well as a complex list of compliance measurements. Evaluating a simple matrix resulted in over 300 variations that required analyses and numerous calculations. To design for faster speeds, SECO’s designers required a change in their design flow. They also needed an easier setup methodology to achieve a fast time to market.

An Easier Setup Methodology

To avoid a potentially costly misstep, such as a release delay or product recall, the company needed to correctly model its entire design layout and simulate for DDR4. In the past SECO followed the layout design guide provided by its silicon vendor, but in some cases, that still led to board design failures. Moreover, it became too time-consuming to analyze 300 design variations through matrices alone. SECO required a simulation software that could accurately characterize its DDR4 board with all its components, high-speed interfaces, and interactions.

The solution came in the form of Keysight Technologies’ PathWave Advanced Design System (ADS) design and simulation software (Figure 1). PathWave ADS not only minimizes the engineering effort required to set up simulations, extract high-accuracy electromagnetic (EM) models of the PCB, perform system simulation of the buses, and perform compliance testing. It also provides an entire high-speed digital design workflow, all within one software suite.

PathWave Memory Designer, a simulation element within PathWave ADS, offers a unique capability to use the same measurement science for both simulation and hardware verification stages. This capability eases the simulation to the measurement comparison process. Using PathWave Memory Designer, SECO’s designers built-out complex models in just 15 minutes. The designers also used SIPro and PIPro, other simulation elements within PathWave ADS, to perform EM extractions.

A Faster, Stronger Design Flow

Using PathWave ADS, SECO designers quickly evaluated the system margin of a complex embedded motherboard. They completed a statistical and transient simulation within just a few minutes. In the transient simulation mode, the simulated waveforms were fully automated and handed over to the oscilloscope compliance measurement suite, which then read the voltage and timing settings from the simulation. Setup and hold times, jitter values, and over and undershoot values were recorded in a report for easy and fast review (Figure 2). SECO designers achieved a robust design with increased error margins.

With simulation software, the designers at SECO were able to decrease the number of board failures to zero. Before using PathWave ADS, they reported that 20% of their PCB prototypes would fail, even after re-spins. They now report having zero issues related to DDR or SI failure. Using SIPro and PathWave Memory Designer, the designers decreased their design optimization time by ten days. The designers require just 30 days to reach design sign-off for a new DDR design, thus decreasing their overall design time by 35% compared to their previous design flow.

Looking Ahead to DDR5 Design

The PathWave ADS software provided SECO both increased confidence in its designs and the ability to eliminate board failures due to DDR and SI issues. It can now better optimize its designs for quality and money and do so in a shorter amount of time. SECO also decreased its overall design optimization time by 35% and achieved its time-to-market goals.

Using PathWave ADS, SECO can continue providing pioneering digital technologies that increase value to its customers. Also, it has a stronger, faster design workflow to design for DDR4 and beyond (Figure 3).

Upcoming DDR5 systems plan for bandwidth, memory capacity, and speeds to practically double from that of DDR4. Power efficiency will also improve. Increasing the speed of serial data communications requires high-speed precision design and test at every level, as well as in-depth analysis of signal and power integrity. PathWave ADS offers SECO and other signal integrity engineers an end to end design and simulation flow that can handle the complexities of DDR4 and beyond.