W2307EP Interconnect Toolbox Element

W2307EP Interconnect Toolbox Element

Design Your High Speed Channel for Metrics That Matter

Transmission lines and via transitions form the high speed signal path between a transmitter and a receiver. These paths are known as PCB (Printed Circuit Board) interconnects, and if not optimally designed they can easily destroy the signal integrity of a link. The eye metrics are heavily impaired by both loss, and reflections in the system. Advanced Design System (ADS) offers signal integrity simulation tools to help explore design trade-offs and manage the complex interactions between substrate stack-up, transmission line losses, and via topology. The W2307EP Interconnect Toolbox Element contains two utilities for the design of high-speed interconnects– Via Designer Utility and the Controlled Impedance Line Designer Utility. ADS additionally provides the Substrate Editor, which all-combined together offer a design methodology to achieve optimal link designs.

Controlled Impedance Line Designer

The Controlled Impedance Line Designer (CILD) Utility enables you to optimize your PCB stack up and transmission line geometry using metrics that matter, namely postequalizer eye diagram parameters. Other tools will show you the impairments of the lines, such as loss, frequency roll off, and impedance variation, but in today’s multi gigabit chip-to-chip links these metrics are inadequate. What really matters is the eye parameters after the line impairments have been mitigated by the signal processing in modern Serializer/Deserializer (SerDes), for example transmitter (Tx) pre-emphasis and receiver (Rx) equalization. In fact, the whole point of the signal processing in the I/O of modern chips is to allow you to use lower cost materials and yet still open the eye. The CILD Utility achieves this by letting you place a Tx and Rx around the candidate line to form a complete ADS Channel Simulator or ADS Transient Simulator schematic. The statistical mode of Channel Simulator can yield ultra-low BER contours in seconds per point in the design space. You can quickly sweep parameters such as width and spacing to see the effect.

Via Designer

The Via Designer Utility enables you to quickly design both single-ended and differential via transitions, driven from a graphical user interface. Your via models can be fully parameterized and analyzed with highly accurate 3D full-wave, Finite Element Method (FEM) simulation technology. The simulation results can be viewed within the utility (mixed-mode S-parameters), and the parameterized model can be exported for use in channel simulation. The extracted model contains a compact database of parameterized results allowing for efficient interpolation between simulated data.

Signal Integrity Challenge - Finding the margin eaters

Today’s signal integrity design challenge is not just to successfully recover the transmitter signal at the receiver, but to understand what is controlling the performance. What are the significant margin eaters and which ones can you optimize? Here we see the potential problem of leveraging vendor supplied reference designs or past product designs when the PCB stack-up is not the same. The leveraged via design results in a closed eye. A quick 15-minute optimization in ADS provides an engineered solution with well understood design margins. Designing the PCB interconnect starts with a preliminary PCB stack-up definition, followed by an evaluation of transmission line topologies, and then locating the vias that transition between layers. Anyone of these steps has cost and performance trade-offs that can impact the other, resulting in a complex interrelationship to determine which feature is the real margin eater: Layer Count, Line Z, Via Backdrills, Material parameters (Dk, Df, roughness, etc), Layout Density…etc.