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IBIS-AMI modeling for high-speed serial link systems becomes the de facto standard in the industry. The evolution of IBIS-AMI modeling standard started from a pure THRU channel modeling for NRZ signaling and expanded to the inclusion of crosstalk aggressors, to links containing repeaters, to back-channel transmitter (TX) and receiver (RX) equalizer training process, to the modeling of PAM4 and duobinary signaling.
However, to date IBIS-AMI modeling can only deal with a synchronous system, indicating that the TX and RX share a common reference clock source. In real applications, there are many more systems that are designed for asynchronous operations, i.e., there exists certain frequency offset between the reference clocks for the transmitter and the receiver. Thus, clock-data-recovery (CDR) behavior in the case of frequency offset between the TX and the RX is not verified through the standard IBIS-AMI simulation. As a result, the impact of the frequency offset is not rigorously evaluated, leading to potential overoptimistic estimation of system performance.
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