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Keysight Technologies
Testing of Small Form-Factor Products
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Testing of Small form-factor Products
Boundary scan and embedded test will need to make up for ICt gaps.
Small form-factor (Sff) mobility products have spurred massive on-chip integration of CPU, graph-ics, memory, and multiple communication standard interfaces, ranging from wired to wireless onto a single system-on-chip (SoC) package. The printed cir-cuit board assemblies of these products are extremely dense with memory and storage components soldered down, eliminating bulky connectors to fulfill the “thin” features. PCBs for SFF mobility products pose new manufacturing challenges such as package-on-package SMT assembly and limited real estate for test pads. Diminishing accessibility to probe circuit nets for testing, debug and diagnostics requires a test strategy rethink and updated design for test (DfT) guidelines.
A typical PCB for such SFF products will be lit-tered with 01005 component packages, and the SoC is most likely a BGA with over 1,000 solder balls below the package. The SMT process will benefit from using the full range of AOI equipment:
While automatic x-ray inspection can inspect hid-den solder joints, especially under SoC BGAs and any PoP, implementation is cost-prohibitive.After SMT, the PCBA risks are shorts and opens on hidden solder joints (if AXI is not implemented) and powered shorts. Electrical test will need to pro-vide test coverage for these gaps.It is inconceivable to design a board with no test access, as power (all on-board voltages) and ground need to be validated, especially when diagnosing board failures. Together with the power and ground nets, critical signals like inputs, outputs and control lines should be given test access for the same reasons. This is the minimum test access to assess PCB func-tionality. Test access enables the process of elimina-tion to find the root cause of a failure; generally more test access is preferred to less.
Diagnosing and identifying the defect within the PCBA will need to focus on key components like SoC and memory. Most SoC are IEEE 1149.1 (boundary scan) enabled, and access to its test access port (four nets) expands shorts and opens test coverage to its thousands of hidden solder joints. Boundary scan is a very efficient and productive test methodology for large pin count BGAs. Innovative boundary scan test extensions increase test coverage to components con-nected to the SoC. These components can be memory, storage, communication and sensor hubs.
Some SoC suppliers like Intel offer proprietary test technology for Haswell microarchitecture CPU designs. Intel SVT, for instance, enables test of the Haswell SoC CPU, its functions and connectivity to the surrounding peripheral components through a custom debug port (12 nets and four nets for bound-ary scan TAP). It is extremely effective for SFF designs constrained by real estate or high-speed signal fidelity.
Using Intel SVT as an example of SoC embedded testing, test coverage can be extended to (Figure 1):
Assumptions:
Boundary scan and embedded test will most likely require fewer than 20 probes, and the equipment to perform the tests is a PC controller (or a notebook PC) with a boundary scan box, benchtop power supply, cables and connectors. This test can easily start its life in an R&D lab on prototype boards and then be reused in its entirety in manufacturing, either as a separate standalone station or incorporated with ICT.The objective of an SFF product manufacturing test strat-egy is to optimize test coverage and provide useful diagnos-tics to enable efficient repair with minimal test accessibility. ICT has been the de facto test deployed in manufacturing. Diminishing test access in SFF will reduce its effectiveness. The loss of ICT coverage and diagnostics has to be recovered by the addition of boundary scan and embedded test.
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