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U4154B Logic Analyzer Module 4 Gb/s State Mode

Data Sheets

Keysight Technologies

U4154B Logic Analyzer Module

4 Gb/s State Mode

Data Sheet

Introduction

Product Description

The Keysight Technologies, Inc. U4154B logic analyzer system combines reliable data capture with powerful analysis and validation tools to enable you to quickly and confidently validate and debug high-speed digital designs operating at speeds up to 4 Gb/s.

Figure 1A shows the small Read DQ eyes associated with a DDR4 system operating at 2400 Mb/s data rate. This screen shot is captured in signal trace mode with no back-to-back bursts so that the eyes for the entire burst of 8 are displayed. The U4154B logic analyzer uses its unique eye scan capability to automatically place the sampling point in both time and voltage within the eye on each individual channel for optimal sampling reliability.

Figure 1B shows the trigger setup to capture a burst of 8 data samples. The trigger sequencer operates up to 2.5 GHz, enabling accurate and precise triggering.

Figure 1C and Figure 1D show the state listing and waveform for these data captures. The 12.5 GHz Timing Zoom with 256 K sample memory gives you simultaneous state and high-resolution timing measurements covering a time span of 20 µs, which corresponds to 43680 clock cycles at a 2133 MHz clock rate.

Available memory depth up to 200 M samples allows you to debug very complex problems where the cause and symptoms may be separated by several seconds. The amount of memory can be upgraded after purchase; see the Upgrades section of the Ordering Information on page 16.

No need to sacrifice sampling resolution to view more system activity. In timing mode, if your system has bursts of activity followed by times with little activity, you can use transitional timing along with the logic analyzer’s deep memory to capture seconds to minutes of activity at 400 ps sampling resolution at a sample frequency of 2.5 GHz. You also have the flexibility to increase the amount of time captured by excluding certain buses or signals from the transition detector. For example, you can exclude clock or strobe signals that add little useful information to the measurement. In State mode, select Store Qualification to save only states of interest into memory.

The dual-sample mode for DDR memory signals up to 2.5 Gb/s allows for the separation of reads from writes with automatic setup of the correct sampling positions for each. Dual sample mode also allows acquisition of state (synchronous) data at rates up to 4 Gb/s. When used in this mode, the data will appear in two labels. One label for rising edge and another for falling edge captures. The logic analyzer will be clocked with one edge of the system clock. Labels can be merged using the Keysight B4602A Signal Extractor tool. When operated in dual-sample mode on all pods, the channel count is 68 channels for one U4154B 136 channels for two U4154Bs, or 204 channels for three U4154B modules combined. Dual-sample mode can be selected on a per-pod-pair basis, so if you have only a subset of signals that require dual-sample mode, the channel count can be higher.

For DDR2/3/4 and LPDDR/2/3/4 memory solutions under 2.5 Gb/s data rates, dual sample mode is used to separate read and write data traffic. The B4621 DDR2/3/4 decoder or the B4623B LPDDR/2/3/4 decoder reassembles the data to align with the associated commands. (There’s no need for the B4602A tool for DDR and LPDDR solutions.)

For DDR4 and LPDDR4 memory solutions over 2.5 Gb/s, double probing is required to capture Read and Write DQ signals and dual sample mode is used to capture rising and falling edge DQ samples. Using this technique, a maximum of 34 DDR4 or LPDDR4 DQ signals operating over 2.5 Gb/s can be captured per U4154B module. Address, command, and control signals for DDR or LPDDR memory do not require double probing above or below 2.5 Gb/s data rates.

A burst-mode clock allows you to take measurements that include periods of inactivity on the clock, such as power management transitions when the clock is inactive.

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