How to debug the 3 differences that are encountered on the new hybrid pin cards (P/N: E4000-66562 and E4000-66563)?

Follow the guideline to debug your test when you start using the new bybrid pin cards:

• E4000-66562 for 6 MPs (standard hybrid pin card)
• E4000-66563 for 12 MPs (advanced hybrid pin card)

1. Slower transience for receiver pull-up/pull-down

The pull-up or pull-down load setting used on the receiver of the ASIC to tie a floating pin on the device under test (DUT) during the digital test exhibits slower transience (Figure 1).
Resolution steps:

a) Execute “Diagnose Fault, Verbose”
b) After execution, the “Diagnose Fault, Verbose” option will suggest changes. (Figure 2)
c) The changes could be in the Vector cycle or Receive delay, “rh or rl”, “slew rate”, “dh or dl”, “slew rate”, “pull up/pull down” and “noload”.

Note: User can evaluate other test options manually, such as changing the “rh” or “rl”. This step is similar to debugging a digital test for different IC Vendors.
 

                                   Figure 1: Slower Transient

                       Figure 2: Diagnose Fault, Verbose suggestion

Example of failure message and resolution:

 2. Higher sensitivity in the over-voltage protection

The new pin card exhibits higher sensitivity in the over-voltage protection feature due to the difference in the driver/receiver IC design technology. The new IC uses the CMOS technology versus the obsolete BJT technology in the previous ICs used.
When a test fails over-voltage, three conditions are always satisfied:

1. When an upstream device is driving a “1” and
2. The test is over-driving with “0” at the DUT input pin and
3. The next vector demonstrates a “Z”, or the system may automatically disable the driver and receiver due to ending of the digital test.
In this scenario, do note that the resolution step “Diagnose Verbose” will not help resolve the situation. Instead, the following steps are recommended:

A. If the failure is not on a disable node and over-voltage occurs in the last vector:

i. If the over-voltage protection failure is at the last vector, where possible, swap vectors or units so that the failed input pins are not being over-driven to “0” at the last vector of the digital test.

Example of the failure message:
u359 HAS FAILED
15-6424-01 IC-LOGIC,GTL2005,GTL to LVTTL
vector near 17
Status: 193H
Stopped on halt instruction
Sequencer halted due to fatal error
Fatal error on module: 0
Overvoltage on following input pins:
BRRCC NODE PIN
107165 AG_TDO_3V3_PCH0 U359.9
Sequencer halted

ii. Or, add a vector to drive the failed input pins to “1” as the last vector

B. If the failure is on a disable node and over-voltage occurs in the last vector:

Add a vector to drive the disable node to ‘1’ as the last vector of the digital test.
Example: A new vector “Dis_Node_1” is added into a new unit “Dis_Hi” which is placed at the end of the digital test. The vector “Dis_Node_1” sets the disable node “PIT_RST-” to “1” as the last vector.

C. If the over-voltage occurs in between the vectors:

Change the “Z” state after the over-drive “0” vector to “1”.

If the failing test is in PCF format, please note the additional recommended steps below:

i. Identify the failed pin from the failure ticket and locate its position in the “pcf order”.
ii. From the push button debug window, display vector graphics by selecting “Display Actual”, followed by “Display Start at”, to show the failing vector number as shown in the failure message.
iii. Scroll forward or backward in the vector graphics or in the test source window to identify the nearest vector when the input pin changes from “0” to “Z”.
iv. Modify “Z” to “1”.

3. Difference in “Tri-State” Characteristic

Both the current and new pin card can exhibit a voltage glitch whenever a pin driver comes out of tri-state mode either at the beginning of the test or in the middle of a test. In the case of new pin card, this effect is more pronounced, and under certain circumstances, can trigger a logic error in the DUT (IC). As can be seen from figure 2, the timing mismatch between driver enable and driver input signals results in a propagation delay of 30 ns – 50 ns during which a logic glitch can occur.

                       Figure 1: Driver output connected to node/pin of DUT.

Figure 2: Diagram of short propagation delay (30-50 ns) between driver enable and driver output.

Observation 1:

A positive voltage glitch occurs in the middle of a test when a pin driver is enabled from tri-state mode. The pin driver gives a “high” logic output prior to the pin driver being disabled (tri-state) with “x” or “z”. The pin driver remained on “high” logic even when disabled. When the pin driver is enabled subsequently, the pin driver gives a “high” logic output for 30 to 50 ns before it changes to “low” logic. (see figure 2, obervation 1 a, b and c)

As shown in the above observation 1d in figure 2, at pin driver disable state, the node logic of the IC is pulled “low”. When the pin driver is enabled, the node logic of the IC is “high” for a short period before it changes to “low”. This glitch may cause the IC test to fail.

A failure message similar to that triggered by the receiver pull-up/pull-down transience issue described earlier will be displayed. When “Diagnose verbose” is executed, the tool may recommend the user to ‘set the default states for all input pins in VCL source to “K” with assign’.

Example:

Please do not follow the recommendation from the failure message. Instead, you can resolve the issue by modifying the all the input pins with “X” or “Z” state to “K” in the “KEEP” vector. Do not change any output pins.
 

Observation 2:

For certain digital tests situations, the node of the device under test (DUT) (e.g. reset pin) or upstream device (e.g. disable pins) is required to be maintained on “high” throughout the test. Due to this glitch (30-50 ns) at the beginning of the test, the DUT may reset and the upstream device may enable. Thus, this reset/enable causes the DUT to fail. 

             Figure 3: Diagram shown voltage glitch

Resolution: (Note: “Diagnose verbose” is not helpful in this case.)

Identify the reset or disable signal in the test and change the ‘drive low voltage’ of the node to a value close to ‘drive high voltage’, e.g. if drive high is 3.3 V, drive low can be changed to 2.9-3.0 V. By doing that, the short glitch of logic “0” is on a high voltage, hence, the IC will not fall into reset state and the test will pass. Modified tests are backward compatible.

Observation 2a)
If failure caused by glitches on Reset pin

Example:

The original boundary scan node “SMC_RST_N” needs to be driven high all the time-- drive high voltage is 3.3 V, and drive low voltage is 0 V.

Add “set ref on nodes "SMC_RST_N" to dl 3.0” after the input/output definition and recompile the test.
 

Observation 2b)

If failure cause by glitches on upstream device disable pin
 

Example:

U56 is an upstream device of U55 SPI test. U56 disable node “GLAN1_DEV_OFF_N” needs to be driven high all the time during U55 SPI test. U55 test is a test to capture and read data from the serial flash and compare the data in the testplan. The test itself did not fail; it was only failing the comparison in the testplan.

Add “set ref on nodes "GLAN1_DEV_OFF_N" to dl 3.0” after the input/output definition and recompile the test.