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High Speed Digital Design Seminar: New features and capabilities of ADS 2020 for DDR and SerDes
High Speed Digital Design Seminar: New features and capabilities of ADS 2020 for DDR and SerDes

Seminar Materials 2019-08-21

MIPI C-PHY: Solving Simulation Challenges
MIPI C-PHY: Solving Simulation Challenges

Seminar Materials 2019-08-15

PDF PDF 2.98 MB
Avoiding Power Delivery EMI/EMC Issues through Design Best Practice
Avoiding Power Delivery EMI/EMC Issues through Design Best Practice

Seminar Materials 2019-08-15

PDF PDF 5.11 MB
Designing for DDR4 and Beyond
Designing for DDR4 and Beyond

Seminar Materials 2019-08-15

PDF PDF 8 MB
Advanced Via Designer in PathWave ADS 2020
Advanced Via Designer in PathWave ADS 2020

Seminar Materials 2019-08-15

PDF PDF 2.13 MB
Simulation-to-Masurement Challenges and Solutions for 400GB Ethernet PAM4
Simulation-to-Masurement Challenges and Solutions for 400GB Ethernet PAM4

Seminar Materials 2019-08-15

PDF PDF 5.29 MB
Channel Operating Margin (COM)
Channel Operating Margin (COM)

Seminar Materials 2019-08-15

PDF PDF 983 KB
PathWave Design Seminar: Design a Smaller, Lighter, and Lower Cost Switched Mode Power Supply
The increasing demand for reliable, low cost, high power density power electronics is driving up the edge speed (di/dt) of switched mode power supplies. In this high di/dt era, layout parasitics become increasingly troublesome. Traditional design techniques are not adequate. A new methodology that adds post-layout design and simulation is required. In this seminar, we will present four papers that address these challenges.

Seminar Materials 2019-08-14

IMS 2019 - Show Guide
IMS 2019 - Show Guide

Seminar Materials 2019-05-30

PDF PDF 1.56 MB
Board Test User Group Meeting - May 9, 2019
Download the presentations from the May9, 2019 User's Group meeting in Cleveland

Seminar Materials 2019-05-09

High Speed Digital Design Seminar: New features and capabilities of ADS 2019 U1 for DDR and SerDes
High Speed Digital Design Seminar: New features and capabilities of ADS 2019 Update 1 for DDR and SerDes

Seminar Materials 2019-04-10

Accuracy Matters
What do you do with the result after you take a measurement? Often, people compare the result to a specification and make a “Pass” or “Fail” decision to ship or reject the item under test. They don’t teach you in school how accuracy affects the risk of incorrect Pass/Fail decisions. We will.

Seminar Materials 2019-03-14

PDF PDF 1.59 MB
Webcast: DDR 5.0 - Understanding the Test Ramifications of DDR5
Webcast: DDR 5.0 - Understanding the Test Ramifications of DDR5

Seminar Materials 2019-02-18

EM for Your RF/Microwave Circuit Designs Workshop
Materials for the EM for Your RF/Microwave Circuit Designs Workshop.

Seminar Materials 2019-02-05

Advanced Measurement Techniques for PCIe 5.0 T x/Rx Test
Advanced Measurement Techniques for PCIe 5.0 T x/Rx Test

Seminar Materials 2019-01-23

Solving Power Integrity & Signal Integrity Design Challenges Seminar
Solving Power Integrity & Signal Integrity Design Challenges Seminar

Seminar Materials 2018-12-20

PAM4 and TDECQ Transmitter Testing
PAM4 and TDECQ Transmitter Testing PDF - NDC Post Event Literature

Seminar Materials 2018-10-26

PDF PDF 4.55 MB
Optimizing and Troubleshooting Closed Loop Performance
There are many textbooks, papers, and materials on closed-loop control design for switched-mode power supplies (SMPSs). In this paper, you will learn about mechanisms which cause designs to diverge from a typical textbook closed-loop performance, new techniques which can provide insights into problems, and how to correct issues before fabrication through an improved workflow.

Seminar Materials 2018-10-10

PDF PDF 4.59 MB
Controlling Parasitic Effects
Post-layout parasitic effects that degrade performance and can cause failure — skin depth, proximity effect, spike/surge voltage (sometimes called conducted EMI), noise, ringing, oscillations, and false triggering. All physical implementations include these parasitics to some extent, and their impact is not visible with pre-layout schematic circuit simulation. You will learn how to use ADS and high-speed design techniques to verify, troubleshoot, and optimize your post-layout design.

Seminar Materials 2018-09-20

PDF PDF 3.11 MB
Understanding and Controlling Conductive EMI
High-speed switched-mode power supplies produce noise (conducted and radiated EMI) that can interfere with other electronics and degrade system performance and reliability. Also, this circuit must function correctly even in the presence of inbound interference from its environment, again both conducted and radiated. In this paper, we advocate a different approach; post-layout simulation of EMC as part of the design process.

Seminar Materials 2018-09-20

PDF PDF 6.60 MB
Designing Switched-Mode Power Supplies in the High di/dt Era
Engineers building switched-mode power supplies into their systems demand lower cost, smaller size, and lighter weight. Three components dominate the design challenge: the heat sink, the inductor, and the capacitor. Traditional workflows don't work in the high di/dt era because they are blind to the spike voltages induced across layout parasitics. This paper discusses a post-layout analysis step to the workflow between the pre-layout circuit simulation and physical prototyping steps.

Seminar Materials 2018-09-20

PDF PDF 2.38 MB
Establish a Robust Signal Integrity Measurement and Simulation Workflow Webcast
Establish a Robust Signal Integrity Measurement and Simulation Workflow Webcast

Seminar Materials 2018-09-13

Designing Switched-Mode Power Supplies in the High di/dt ERA Slides
Slides from the September 6, 2018 webinar

Seminar Materials 2018-09-06

PDF PDF 4.35 MB
Build Your RF PCB to Specs and Improve Yield 10x Faster Webinar Slides
Slides from the August 23, 2018 webcast

Seminar Materials 2018-08-23

PDF PDF 3.05 MB
Part 2 - Demystifying Vias in High Speed PCB Design
Slides from the August 8, 2018 webcast

Seminar Materials 2018-08-08

PDF PDF 1.94 MB

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