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Board Test User Group Meeting - May 9, 2019
Download the presentations from the May9, 2019 User's Group meeting in Cleveland

Seminar Materials 2019-05-09

5G NR Technology Overview
Slides

Seminar Materials 2019-05-01

PDF PDF 5.52 MB
High Speed Digital Design Seminar: New features and capabilities of ADS 2019 U1 for DDR and SerDes
High Speed Digital Design Seminar: New features and capabilities of ADS 2019 Update 1 for DDR and SerDes

Seminar Materials 2019-04-10

Signal Integrity Measurements and Network Analysis
This section will briefly touch on transmission line fundamentals and then focus on practical ways to troubleshoot and improve physical layer components inside the internet infrastructure. Topics will include differential s-parameters, how mode conversion relates to crosstalk, practical de-embedding methods to increase accuracy and finally a backplane design case study demonstration using a multiport VNA.

Seminar Materials 2019-04-03

PDF PDF 5.45 MB
Fundamentals of Bit Error Ratio Testing
This section covers receiver testing using a Bit Error Ratio Tester (BERT), the typical applications to use a BERT, and what are the key specification to take into consideration when configuring one. In addition, we will be covering the test setup, how to run a typical receiver test, and how the data test pattern is stressed.

Seminar Materials 2019-04-03

PDF PDF 1.51 MB
Fundamentals of Arbitrary Waveform Generation
This section gives an overview of the use and importance of an Arbitrary Waveform Generator and how to make sure you have the right Sampling Rate and Memory depth to meet your measurement needs when choosing an AWG. Topics will include key specifications of Arbitrary Waveform Generation, the importance of considering filtering and sampling rate, overview about generating signal impairments and customization of your signal with an AWG.

Seminar Materials 2019-04-03

PDF PDF 4.05 MB
High-Speed Oscilloscope Fundamentals
This section will focus on becoming familiarized with oscilloscopes and probing technology from the ground up. Topics will cover sampling rates, bandwidth and aliasing, triggering, waveform visualization tools, waveform update rate, and probing tips and tricks.

Seminar Materials 2019-04-03

PDF PDF 2.99 MB
400G: Looking Forward to 800G
Most of the work on the '400G Class' Standards is complete, and new projects are starting to define the electrical links that will enable the next '800G Class' of optical and electrical standards. The low margins we see today will be even smaller or non-existent in the next generation. Verifying compliance for 400G requires careful attention to test setup and execution and will likely require even more discipline moving forward. This session will cover practical techniques to minimize some of the problem areas users are experiencing today in validating compliance in 400G links, and what challenges we may see as the '800G Class' Standards begins to take shape.

Seminar Materials 2019-04-02

PDF PDF 1.87 MB
Terabit Communication Research with Coherent Optical Modulation Tools
If you plan to use coherent modulation for higher bit rates, this presentation introduces you to the basic concepts of coherent signal measurements, new advanced tools, and provides examples of measurements.

Seminar Materials 2019-04-02

PDF PDF 2.67 MB
PCI Express 5.0: Full Speed Ahead! Phy Layer Testing Challenges at 32GT/s
In this presentation, you'll learn not only what's new with the PCIe 5.0 standard but also what to look for as you evaluate tools to help you validate your transmitter and receiver circuits.

Seminar Materials 2019-04-02

PDF PDF 2.09 MB
TDECQ for PAM4 Optical Transmitters: Does it Really Work?
The use of PAM4 and forward error correction led to dramatic changes in the test methods used to characterize optical transmitters used in digital communications systems. TDECQ (transmitter dispersion and eye closure quaternary) is the primary example of this change. Does the measurement really provide the results it was intended to yield, specifically the power penalty metric needed to predict how well a transmitter will operate in a real system? This paper will try to document when it does and when it does not.

Seminar Materials 2019-04-02

PDF PDF 2.38 MB
Get Your Game On for Next Generation DRAM: DDR5 and LPDDR5
This presentation will show you how to get your game on so you can master a whole new generation of DRAM.

Seminar Materials 2019-04-02

PDF PDF 1.20 MB
A Practical Guide to Signal Integrity: From Simulation to Measurement
If you are new to signal integrity, this presentation will give you a head start on your journey, including complimentary example files for continuing your learning. For experienced SI engineers, this presentation is an excellent refresher on the fundamental SI analyses and concepts in both simulation and measurement.

Seminar Materials 2019-04-02

PDF PDF 3.89 MB
Redefining Drive Test for 5G
Slides

Seminar Materials 2019-03-25

PDF PDF 3.33 MB
Accuracy Matters
What do you do with the result after you take a measurement? Often, people compare the result to a specification and make a “Pass” or “Fail” decision to ship or reject the item under test. They don’t teach you in school how accuracy affects the risk of incorrect Pass/Fail decisions. We will.

Seminar Materials 2019-03-14

PDF PDF 1.59 MB
Webcast: DDR 5.0 - Understanding the Test Ramifications of DDR5
Webcast: DDR 5.0 - Understanding the Test Ramifications of DDR5

Seminar Materials 2019-02-18

EM for Your RF/Microwave Circuit Designs Workshop
Materials for the EM for Your RF/Microwave Circuit Designs Workshop.

Seminar Materials 2019-02-05

Advanced Measurement Techniques for PCIe 5.0 T x/Rx Test
Advanced Measurement Techniques for PCIe 5.0 T x/Rx Test

Seminar Materials 2019-01-23

Solving Power Integrity & Signal Integrity Design Challenges Seminar
Solving Power Integrity & Signal Integrity Design Challenges Seminar

Seminar Materials 2018-12-20

Key Measurement Challenges and Case Studies
Slides

Seminar Materials 2018-11-06

PDF PDF 11.12 MB
Designing Switched-Mode Power Supplies in the High di/dt Era Seminar
The increasing demand for reliable, low cost, high power density power electronics is driving up the edge speed (di/dt) of switched mode power supplies. In this high di/dt era, layout parasitics become increasingly troublesome. Traditional design techniques are not adequate. A new methodology that adds post-layout design and simulation is required. In this seminar, we will present four papers that address these challenges.

Seminar Materials 2018-10-11

Optimizing and Troubleshooting Closed Loop Performance
There are many textbooks, papers, and materials on closed-loop control design for switched-mode power supplies (SMPSs). In this paper, you will learn about mechanisms which cause designs to diverge from a typical textbook closed-loop performance, new techniques which can provide insights into problems, and how to correct issues before fabrication through an improved workflow.

Seminar Materials 2018-10-10

PDF PDF 4.59 MB
Designing Switched-Mode Power Supplies in the High di/dt Era
Engineers building switched-mode power supplies into their systems demand lower cost, smaller size, and lighter weight. Three components dominate the design challenge: the heat sink, the inductor, and the capacitor. Traditional workflows don't work in the high di/dt era because they are blind to the spike voltages induced across layout parasitics. This paper discusses a post-layout analysis step to the workflow between the pre-layout circuit simulation and physical prototyping steps.

Seminar Materials 2018-09-20

PDF PDF 2.38 MB
Controlling Parasitic Effects
Post-layout parasitic effects that degrade performance and can cause failure — skin depth, proximity effect, spike/surge voltage (sometimes called conducted EMI), noise, ringing, oscillations, and false triggering. All physical implementations include these parasitics to some extent, and their impact is not visible with pre-layout schematic circuit simulation. You will learn how to use ADS and high-speed design techniques to verify, troubleshoot, and optimize your post-layout design.

Seminar Materials 2018-09-20

PDF PDF 3.11 MB
Understanding and Controlling Conductive EMI
High-speed switched-mode power supplies produce noise (conducted and radiated EMI) that can interfere with other electronics and degrade system performance and reliability. Also, this circuit must function correctly even in the presence of inbound interference from its environment, again both conducted and radiated. In this paper, we advocate a different approach; post-layout simulation of EMC as part of the design process.

Seminar Materials 2018-09-20

PDF PDF 6.60 MB

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