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What is the raw jitter tolerance for the N4960A/N4952A?
There is no CDR in the N4960A, so by itself, the JTOL plot will be a flat line somewhere below 1 UI. An external CDR can be used. Click on the question for additional information.

FAQ 2017-06-28

If we use external clocks for both the Pattern Generator and Error Detector parts, can we run them at different data rates?
It would be more straight-forward to provide the PG (TX) with a 10 GHz clock (for 10 Gb/s data) and then use the 1:4 demux and provide the ED (RX) with a 2.5 GHz clock (measuring 2.5 Gb/s data). Click on the question for additional information.

FAQ 2017-06-28