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Getting the Most Out of DDR4 and Preparing for DDR5 Webcast

1   Hour | Webcast - recorded | Where & When

DDR4 was the first DRAM technology to break the High Speed Digital paradigm that focuses on signal timing and Voh/Vol/Vih/Vil based noise margin analysis. DDR4 speeds demanded an approach more like what’s used in specifying, designing and testing high speed serial interfaces like SATA, USB 3.0 and PCI-Express (up to Gen 3). Timing and voltage thresholds are replaced by eye diagrams, bit error rates and statistical analysis of random jitter and noise, closing a gap between the DDR specification and the behavior of real systems that opened once DDR3 exceeded 1600MT/s. Many memory designers are still climbing this learning curve that is essential to getting the best performance from DDR4 designs at minimum design risk and cost. Right on the heels of DDR4, DDR5 moves the bar even higher to reach speeds where the data eye is completely closed, requiring advanced equalization techniques to open the eye and assure reliable data transfer. This webcast will help engineers better understand the concepts underlying the DDR4 specification and get the maximum benefits of having a specification that models real system behavior. Then we will extend the discussion to DDR5, to prepare architects, design, and test engineers to take full advantage of its advanced capabilities.


Perry Keller,
Memory Applications Program Manager

Perry Keller is the team lead for Keysight Technologies Digital Applications and Standards Program and Manages its Memory Applications Program. He represents Keysight on the JEDEC and Universal Flash Storage Assn. Boards of Directors and is Chairman of the JEDEC JC40.5 and JC64.5 Logic and UFS Validation Committees as well as the UFSA Compliance Committee. Perry joined Hewlett Packard in 1980 after graduating from Rice University with a Master’s Degree in Electrical Engineering. As HP’s T&M Group evolved into Agilent and then Keysight Technologies, he has served in project management, architecture and R&D roles for hardware, software and ASIC development as well as marketing and product planning for high performance instruments and applications. He lives in Breckenridge, Colorado, and enjoys skiing and mountain biking.

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