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High Speed Digital Seminar Tour 2018

Technical experts and application engineers will demonstrate the most advanced design and test solutions for PCIe Gen 4/5, 400G/PAM4, and signal integrity measurement challenges. Our broad expertise is built on continuing involvement with industry experts, and our high-speed digital test solutions span across all stages of the design cycle: design and simulation, analysis, debug, and compliance testing.

Learn the latest techniques to help uncover problems, optimize performance, and deliver your design on time and within budget.

Register today for a High-Speed Digital Seminar near you. 

COST

Free

CO-SPONSORS

           

WHEN/WHERE

Tuesday, April 10

Keysight Technologies
2250, Alfred-Nobel Blvd.
Suite 102
Ville Saint-Laurent, QC
H4S 2C9

Wednesday, April 11

The Marshes Golf Club
320 Terry Fox Drive
Ottawa, ON K2K 3L1

Friday, April 13

The Westin Prince
900 York Mills Road
Toronto, ON M3B 3H2

Wednesday, April 18

Hilton Vancouver Metrotown
6083 McKay Ave
Burnaby, BC V5H 2W7

AGENDA

Montreal, Ottawa, Toronto Vancouver

8:30 a.m. - Registration/Refreshments

8:55 a.m. - Introduction

9:00 a.m. - Insights and Techniques for Debugging High-Speed Serial Interfaces

10:30 a.m. - Break

10:45 a.m. - 400G/PAM4 - Recent Learnings in Bringing Up 400G Ethernet Links

12:00 p.m. - Complimentary Lunch and Demos

1:00 p.m. - PCI Express: Gen4 Test Challenges and Preparing for Gen5

2:15 p.m. - Break

2:30 p.m. - Establish a Robust Signal Integrity Measurement and Simulation Workflow

3:45 p.m. - Wrap-up and prize draws

8:30 a.m. - Registration/Refreshments

8:55 a.m. - Introduction

9:00 a.m. - Insights and Techniques for Debugging High-Speed Serial Interfaces

10:30 a.m. - Break

10:45 a.m. - 400G/PAM4 - Recent Learnings in Bringing Up 400G Ethernet Links

12:00 p.m. - Complimentary Lunch and Demos

1:00 p.m. - PCI Express: Gen4 Test Challenges and Preparing for Gen5

2:15 p.m. - Break

2:30 p.m. - Establish a Robust Signal Integrity Measurement and Simulation Workflow

3:40 p.m. - Getting the Most Out of DDR4 and Preparing for DDR5

4:20 p.m. - Wrap-up and prize draws

PRESENTATIONS

Insights and Techniques for Debugging High-Speed Serial Interfaces
In this presentation we will look at some powerful debugging and processing tools to help you isolate and debug signal integrity issues in high speed systems. We will break down how these tools are presently used in our compliance automation software, and how you can take advantage of these signal integrity tools in your own lab when doing root cause analysis.

PCI Express: Gen4 Test Challenges and Preparing for Gen5
With demand on networking and computer performance increasing at a rapid pace, there is a growing need to store, move and process more data in real-time than ever before. This presentation will highlight Keysight’s contributions to PCIe® 4.0 test technology. Topics will include physical layer transmitter and receiver testing methodologies, and new tools for testing PCI Express 4.0 devices along with a preview of new test fixtures needed for PCIe 4.0 physical layer testing. We will also highlight the work Keysight has been engaged in with the industry to pave the way towards higher bandwidth and throughput in digital systems including PCI Express to 32GT/s in the 5th generation of that standard. At the Toronto seminar only, special guest presenter Rick Eads, Principal PCI Express Program Manager at Keysight, will also discuss the latest information regarding the status of the PCIe 5.0 specification, new expected capabilities in receiver equalization, channel requirements, and the minimum and optimal requirements for testing PCIe 5.0 with today’s instrumentation.

400G/PAM4 - Recent Learnings in Bringing Up 400G Ethernet Links
As the working groups developing “400G” data center networking standards are finishing up these documents, SerDes and optical module vendors are moving from characterizing initial prototypes on evaluation boards to prototyping the first full operational links. As can be expected with the revolutionary change in modulation from NRZ to PAM4, this can be challenging. This session will cover what we thought we knew about deploying this new format, and surprises we are learning along the way, including measurement challenges characterizing the performance and verifying compliance to the new standards.

Establish a Robust Signal Integrity Measurement and Simulation Workflow
It is no trivial task to make a good measurement. It requires careful calibration of the ports on the instrument, and appropriate application of fixture removal to the device under test. If treated with care, the result of your hard work is more than an accurate high frequency behavioral model of a channel. It is a gateway to a better understanding of serial link performance and channel operating margin. Given proper measurement, analysis and simulation tools, you will be able to extract the material properties, create a channel model and optimize your channel for minimal bit errors. Moreover, with the help of the single pulse response analysis method, the effect of equalization can be studied and configured. In this session, you will learn to establish a robust measurement and simulation workflow and get the most signal integrity insight out of your everyday measurement and simulation process. 

Getting the Most Out of DDR4 and Preparing for DDR5
DDR4 was the first DRAM technology to break the High Speed Digital paradigm that focuses on signal timing and Voh/Vol/Vih/Vil based noise margin analysis. DDR4 speeds demanded an approach more like what’s used in specifying, designing and testing high speed serial interfaces like SATA, USB 3.0 and PCI-Express (up to Gen 3). Timing and voltage thresholds are replaced by eye diagrams, bit error rates and statistical analysis of random jitter and noise, closing a gap between the DDR specification and the behavior of real systems that opened once DDR3 exceeded 1600MT/s. Many memory designers are still climbing this learning curve that is essential to getting the best performance from DDR4 designs at minimum design risk and cost. Right on the heels of DDR4, DDR5 moves the bar even higher to reach speeds where the data eye is completely closed, requiring advanced equalization techniques to open the eye and assure reliable data transfer. This session will help engineers better understand the concepts underlying the DDR4 specification and get the maximum benefits of having a specification that models real system behavior. Then we will extend the discussion to DDR5, to prepare architects, design, and test engineers to take full advantage of its advanced capabilities.