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H7230A #510 3070 Boundary Scan

4.5   Days | Classroom Training | Where & When | Advantages of Keysight Training


Class Date Loaction
Production Support Jun 13-17, 2016 Cleveland, OH
Boundary Scan Mar 27-31, 2017 Santa Clara, CA

Audience: Keysight i3070 programmers who need to test Boundary Scan devices on their printed circuit boards.
NOTE: This class has been completely updated in 2010.

What you will Learn

  • This class de-mystifies Boundary Scan for i3070 Programmers (Technicians and Engineers):
  • Learn concepts of Boundary Scan technology (IEEE STD 1149.1 with an added discussion of 1149.6 Differential Pair testing).
  • The architecture of the TAP (Test Access Port), the functionality of the various registers (Bypass, Boundary, IDCode…) and how the test controls those registers.
  • The Boundary Scan instructions such as EXTEST, BYPASS, Sample/Preload...
  • Learn to read the industry standard Boundary Scan Description Language (BSDL).
  • The Macros of the Scan Port Driver (state diagram) are used to develop an Incircuit Boundary Scan test for stand-alone Boundary Scan devices: develop, turn-on and debug.
  • Develop Simple Setup and Setup and Disable libraries for Boundary Scan devices. Learn when to use each and why!
  • Advanced Boundary Scan topics are described: Develop Boundary Scan Chains, BSDL files are used with the Scan Port Driver to create libraries. These are developed into tests (Powered Shorts, Interconnect, Bus Wire, Connect and Disable). Turned-on and debug all of these tests.
  • More Advanced Boundary Scan topics are added:
  • Silicon Nail is described and tests developed, turned-on and debugged.
  • Advanced I/O (aka 1149.6 Differential Pair) testing is described in lecture, then a test is developed, turned-on and debugged.
  • Boundary Scan is coupled with VTEP in Cover Extend Technology. This is described in lecture, then a test is developed, turned-on and debugged.
  • Boundary Scan is coupled with Keysight's In System Programming (ISP) software to program a Programmable Logic Device (PLD/CPLD).
  • Hands-on labs provide practical experience reinforcing Boundary Scan concepts. Debug techniques are practiced and diagnostics enhancements are implemented on the Keysight i3070.
  • Advanced testing concepts such as working with a Scan Path Linker and custom RUNBIST and INTEST are discussed.
  • Design For Testability using Boundary Scan technology are included with a visit to Keysight's Access Consultant.
  • Best Practices are discussed - for board design and fixture construction.


  • Electronic Technicians or Engineers
    Keysight i3070 User Fundamentals Classes I (H7230A#500) & II (H7230A#555)


  • Boundary Scan Basics
    • Boundary Scan concepts, purpose (Manufacturing faults, Test generation time reduction, better diagnostics, solution to limited access issues), flexibility, test coverage and ease of use... Yes, Keysight's Boundary Scan is easy to use once the topic has been demystified!
    • Learn to read the BSDL (basic).
    • Learn the unique hardware associated with the Boundary Scan TAP (Test Access Port): Test Data In (TDI), Test Data Out (TDO), Test Mode Select (TMS), Test Clock (TCK) and Test Reset (TRST/), Boundary Cells, Registers and test sequence.
    • Develop a Boundary Scan Incircuit test for a stand-alone part, turn-on and debug that test.
  • Advanced Boundary Scan
    • A description of the Interconnect test: (concept and implementation details)
    • A description of the Powered Shorts test: (concept and implementation details)
    • A description of the Connect test: (concept and implementation details)
    • A description of the BusWire test: (concept and implementation details)
    • Using a board test that is complete except that it excludes any Boundary Scan testing, develop Advanced Boundary Scan tests for chains on the board.
  • More Advanced Boundary Scan
    • A description of the Silicon Nail test: (concept and implementation details)
    • A description of the Cover Extend test: (concept and implementation details)
    • A description of the Advanced I/O (Differential Pair) test: (concept and implementation details).
    • Labs add Silicon Nail, Cover Extend and Advanced I/O testing to the same board used earlier. Turn-on and debug these tests.
    • Boundary Scan specific debug tools are examined in detail: How to debug the VCL test, then edit the Interconnect Test Language file (ITL) so it will create a new VCL with the proper corrections.
  • Other Boundary Scan Topics
    • Custom Boundary Scan tests are discussed. This includes BIST and INTEST.
    • Working with a Scan Path Linker is discussed.
    • Best Practices are discussed. This includes Board Design / Design For Test and fixture design and implementation.
    • Advanced Debug: tools, tricks and skills
    • Scanwork - an overview
    • Coverage Analyst - How Boundary Scan factors into this new Keysight Quality Tool

Where & When

Price Date(s) Location Phone For more information
US$ 2,472 2017-09-11 — 2017-09-15 Santa Clara, CA  +1 800 829-4444 How to Enroll

Prices shown are list prices and are subject to change without notice. Terms & Conditions