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DDR4/LPDDR4 Testing – Best Practices to Get to Market Faster Webcast

1   Hour | Webcast - Registrato | Where & When


Both DDR4 and LPDDR4 present significant test challenges as data rates increase with new test parameters in the JEDEC specification. Best practices will be discussed to address the design challenges, and to demonstrate how to gain greater insight into reference designs, understanding design constraints, and their impact on system margin. When it comes to analyzing the test results, designers and their managers need an intuitive way to visualize the performance and the results of their characterization work.

Attendees will learn how Keysight’s complete DDR4 and LPDDR4 solution will enable them to make faster decisions and reduce time to market of their new designs.


Engineers who need to validate DDR4 and LPDDR4 based designs.


Ailee Grumbine, Strategic Solution Planner, Keysight Technologies

Ailee specializes in high-speed memory technologies such as DDR and SD UHS interfaces. She graduated from the University of Science Malaysia in 2001 and completed a Masters of Business Administration from the University of Colorado, Colorado Springs. Prior to her current position, Ailee was a regional applications engineer with expertise in high-speed bus applications which include DDR memory physical layer and protocol testing.

Where & When

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Free At Your PC Enroll to view the April 20, 2017 recorded broadcast 

Prices shown are list prices and are subject to change without notice.