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Demystify MIPI M-PHY Receiver Physical Layer Test Challenges Webcast

1   Hour | Webcast - enregistré | Where & When


The Mobile Industry Processor Interface (MIPI) Alliance standards body standardizes interfaces for mobile designs. The MIPI D-PHY and M-PHY are introduced as high-speed physical layers serving as base for multiple applications such as camera, display, memory and baseband running protocols such as CSI, DSI, UniPro, LLI and DigRFv4. Other, originally non-mobile, protocols such as USB 3.0 and PCIe are being adapted to work with the M-PHY physical layer as well. Being optimized for both performance (high data rates) and (low) power consumption introduces many new validation (test) challenges outlined in the MIPI Conformance Test Suites (CTS), which are key to system interoperability. D-Phy and M-Phy Rev. 1 & 2 currently support data rates at ~1.5 and ~3 Gbps respectively. The new M-PHY specification rev.3 will be adding Gear 3 support (~6 Gbps data rate), including new requirements such as transmit de-emphasis and more complex Receiver jitter testing. If you are developing or validating these MIPI-M-Phy based RX designs (and /or are a silicon / IP vendor or system integrator), you'll want to attend this seminar to understand how to overcome the physical layer test challenges.


Design, test and validation engineers who need to characterize and validate compliance of their MIPI designs.


Michael Fleischer-Reumann, Expert Product Marketing Engineer, Agilent Technologies

After receiving his Diploma in electrical engineering from the Ruhr-University, Bochum, Germany, in 1980, Michael joined HP in Boeblingen. His R&D work resulted in patents on fiber optic components, electronic circuits and measurement methods. Nowadays with Agilent as planner and application expert for BERTs, he contributed to standardization within OIF, IEEE and PCI-SIG

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Free At Your PC Enroll to view the January 22, 2014 recorded broadcast 

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