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DesignCon 2018 - Keysight Education Forum

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Keysight Technologies is pleased to offer you all 8 Keysight Education Forum (KEF) sessions free of charge. Keysight as the test and measurement experts, continues with KEF 2018 to showcase undeniable leadership across and commitment to the high-speed digital and semiconductor markets.

Great America 1 Conference Room January 31st and February 1st

Session Details Session Title Session Description Session Presenter(s)
Wednesday January 31
8:30 - 9:10am
Single Pulse Response: SI Analysis in the Blink of an Eye - Establish a Robust Signal Integrity Measurement and Simulation Workflow The Single Pulse Response demonstrates the impact a channel has on a single pulse. It reveals a lot of information about the behavior of interconnects, including channel loss, reflections and performance of the equalization. Unlike an eye diagram, which gives you final insight into the margin you have available, the Single Pulse Response is a diagnostic method to extract the information you need to improve your margin. In this session, you will learn about simulating the SPR method with Keysight’s Advanced Design System (ADS 2017), analyzing the result in both time and frequency domain, and how it can be applied to modern PAM4 signaling challenges. 

Chun-ting "Tim" Wang Lee, Application Engineer for High Speed Digital applications in the EEsof EDA Group
Chun-ting "Tim" Wang Lee is an Application Engineer for High Speed Digital applications in the EEsof EDA Group of Keysight Technologies. Wang Lee received his BSEE degrees from University of Illinois at Urbana Champaign and MSEE from University of Colorado at Boulder. He is currently a Ph.D candidate focusing on signal integrity research in the Electric Engineering Department at the University of Colorado. In the past years, he has given talks in DesignCon and involved himself with signal integrity projects focusing on improving simulation and measurement correlation. 

Wednesday January 31
9:20 - 10:00am
Stop Wasting Time and Money by Struggling with Data Analytics While Designing T&M Experiments Data analytics can play a valuable role in the T&M world by accelerating design simulation, analysis, validation, compliance testing and manufacturing. Effective data analytics tools can help engineers improve their design of experiments and reduce the design cycle time - ultimately saving money and enabling your team to get to market faster. This session explains how modern visualization tools provide critical insights and accelerate new designs.

Brad Doerr, R&D Manager Digital & Photonics Center of Excellence
Brad Doerr is the R&D manager for Keysight Technologies’ Digital and Photonics Center of Excellence leading R&D teams in the US, India and Malaysia in the development of oscilloscopes, logic analyzers, probing and software solutions. Mr. Doerr has held leadership roles in HP/Agilent/Keysight since 1988 focused primarily on digital communications and electronic measurement. Mr. Doerr holds BSEE from the University of Minnesota (1988), MSCS Stanford University (1994) and has been granted 3 US patents.

Ailee Grumbine, Strategic Product Planner – Data Analytics
Ailee specializes in data analytics and high-speed memory technologies such as DDR and SD UHS interfaces. She graduated from the University of Science Malaysia in 2001 and completed a Masters of Business Administration from the University of Colorado, Colorado Springs. Prior to her current position, Ailee was a regional application engineer with expertise in high-speed bus applications which include DDR memory physical layer and protocol testing. 

Wednesday January 31
10:15 - 10:55am
What’s New in Testing 400G/PAM4 Transmitter Designs? Most 400G links used in high-speed datacom applications utilize signaling formats such as pulse amplitude modulation 4-level (PAM4) to achieve design goals defined in draft standards such as 400G Ethernet (IEEE 802.3bs and IEEE 802.3cd) and OIF-CEI-56G. The Standards are now stable and nearing ratification, but we know it is often difficult for engineers to stay on top of all the recent changes. Attend this session to learn about the latest updates to new measurements performed on electrical and optical PAM-4 transmitters, and discover new tools that will help you characterize and debug your 400G designs quickly and accurately.

Rob Sleigh, Strategic Planner – Network Data Centers
Robert Sleigh is a Product Manager for sampling scope solutions in Keysight Technologies' Network and Data Center organization. His responsibilities include product development of pulse amplitude modulation 4-Level (PAM-4) test solutions based on Keysight’s high-speed electrical and optical digital communications analyzer (DCA). Robert's experience at Keysight Technologies/Agilent Technologies/Hewlett-Packard includes 5 years in technical support and over 12 years in technical marketing. Prior to working at Keysight, Robert worked for 10 years at Westel Telecommunications in Vancouver, British Columbia, Canada, designing microwave and optical telecommunication networks. Rob earned his B.S.E.E. degree from the University of Victoria.

Greg LeCheminant, Measurement Applications Specialist, Digital Communications Analysis,
Internet Infrastructure Solutions

Greg Le Cheminant is a Measurement Applications Specialist for digital communications analysis products in the Internet Infrastructure Solutions Group. He is responsible for development of new measurement applications for the group’s optical communications test products. He represents Keysight on several industry standards committees. Greg's experience at Keysight/Agilent/Hewlett-Packard began in 1985 with five years in manufacturing engineering, and the remainder in various technical marketing positions. He is a contributing author to four textbooks on high-speed digital communications and has written numerous technical articles on test related topics. He holds two patents. Greg earned BSEET and MSEE degrees from Brigham Young University.

Wednesday January 31
11:05 – 11:45am
Recent Learnings in Bringing Up the First 400G Links As the working groups developing “400G” data center networking standards are finishing up these documents, SerDes and optical module vendors are moving from characterizing initial prototypes on evaluation boards to prototyping the first full operational links. As can be expected with the revolutionary change in modulation from NRZ to PAM-4, this can be challenging. This session will cover what we thought we knew about deploying this new format, and surprises we are learning along the way, including measurement challenges characterizing the performance and verifying compliance to the new standards. 

Steve Sekel, 400G Solutions Specialist, Internet Infrastructure Solutions
Steve Sekel is currently the 400G solutions specialist in the Internet Infrastructure team within the Networking and Data Center division at Keysight. In this role, he guides the requirements definition for solutions and solution components used for characterization and compliance testing of everything within the data center ecosystem involving ‘400G class’ optical and electrical links. Steve currently represents Keysight in the CEI (Common Electrical Interface) project working groups within the Optical Internetworking Forum where is has made several technical contributions to compliance testing specifications and methodology. In the OIF, he also serves as the chair of the Physical and Link Layer Interoperability Working Group. He also is a contributor in the IEEE 802.3bs and 802.3cd projects developing next generation Ethernet links operating in the range of 50 – 400Gb/s. In the past, he has made similar contributions within the 32 G Fibre Channel standard working group. 

Thursday February 1
8:30 - 9:10am
Complete Automation of Type-C Devices The USB Type-CTM connector is being used in portable device designs because of power networking capabilities as well as for its high speed digital transport using USB 3.1, Thunderbolt, and DisplayPort technologies. Though flexible, the Type C interface brings the measurement challenges of multiple standards as well as the complexities of device control to the validation task. This presentation will deal exclusively on how to control the USB Type-CTM interface using a dedicated core solution set. The viewer will understand fundamental capabilities of the interface and how each of the challenges can be addressed to fully characterize any USB Type-CTM device. 

Brian Fetz, Senior Solutions Manager for Display and Measurement Technologies
Brian Fetz is a member of the Wireless Devices Solutions Marketing team and is focused on enabling key digital technologies such as USB3.1 and DisplayPort. Brian graduated with degree in Electronic Engineering from California Polytechnic State University at San Luis Obispo and completed his Master degree in Electrical Engineering at the University of Idaho. His career has focused on Test and Validation. Before joining the marketing team at Keysight, Brian focused in the wireless area for mobile and cell site testers. Most recently he has been responsible for Keysight’s Display Technology solutions including DisplayPort, HDMI, and MHL and currently serves as the Test SubGroup Chairman for the HDMI Forum. He has also been responsible for applied measurement technologies such as Keysight’s embedding and de-embedding software, jitter measurement, and equalization. Most recently, he has led the development of the USB Type C solutions which include the fixtures, application software and power delivery.

Thursday February 1
9:20 - 10:00am
PCI Express 5.0 and the Latest Standards  Technologies such as 400G Ethernet (IEEE P802.3bs) are driving I/O interconnect technologies including PCI Express to 32GT/s in the 5th generation of that standard. Concurrent computing needs, which are elevating co-processor components to the same computer architectural hierarchy as the CPU, are being developed in the Cache Coherent Interconnect for Accelerators (CCIX) consortium and are touching speeds today of 20 and 25GT/s. With this increase in digital transmission speed, the increase in throughput is accompanied by significant signal integrity challenges related to transmitter signal quality, connector crosstalk, receiver jitter sensitivity, and overall channel insertion loss around the Nyquist frequency at which each of these standards operate. In this session, we will bring you the latest information on what Keysight is doing to help develop standards like PCI Express 5.0 as well as other similar standards as far as physical layer testing including transmitter, receiver, and channel testing. In addition, we will describe the latest approach to achieving compliance that uses the same software tools you use for device characterization, but with data provided by simulation instead of physical measurement. The simulation mimics a real hardware test bench and emits the same waveforms the oscilloscope app expects when testing in the lab, which allows for the verification of pre-manufacture simulated design with the actual post-manufacture prototype.

Rick Eads, Principal PCI Express Program Manager, Internet Infrastructure Solutions
Rick is a principal program manager at Keysight Technologies with expertise in technical/industrial marketing of test and measurement tools and electronic design automation software to leaders in the computer, semi-conductor, wired and wireless communications, storage and aerospace industries worldwide.

Rick works on precision product definition and synthesis of breakthrough solutions that address new and emerging needs for both software and hardware products. He provides technical leadership in driving standards within industry organizations for PCI Express, CCIX, GenZ, OCP, NVM Express, CEI 4.0, IEEE 802.3, ExpressCard, DDR, HyperTransport, SATA, and InfiniBand. He has worked in marketing test and measurement products covering oscilloscopes, Logic Analyzers, microprocessor emulation solutions, ASIC emulation tools, and EDA tools.
Rick earned a MBA from the University of Colorado and holds a BSEE from Brigham Young University with an emphasis on digital design and computer architecture.
Rick served on the Board of Directors for the PCI-SIG from 2007-2014 serving as secretary to the PCISIG in 2013 and 2014. Rick actively contributes to the development of the PCIe 4.0 and 5.0 BASE, CEM, and Test specifications and has led electrical Gold Suite testing at PCI-SIG sponsored workshops worldwide since 2004. 

Pegah Alavi, Senior Applications Engineer
Pegah Alavi is a Senior Applications Engineer at Keysight Technologies, where she focuses on Signal Integrity and High-Speed Digital systems. Prior to joining Keysight, Pegah has worked on behavioral and macro-modeling of analog and mixed signal circuits and components in her previous jobs.  

Thursday February 1
10:15 – 10:55am
Establish a Robust Signal Integrity Measurement and Simulation Workflow It is no trivial task to make a good measurement. It requires careful calibration of the ports on the instrument, and appropriate application of fixture removal to the device under test. If treated with care, the result of your hard work is more than an accurate high frequency behavioral model of a channel. It is a gateway to a better understanding of serial link performance and channel operating margin. Given proper measurement, analysis and simulation tools, you will be able to extract the material properties, create a channel model and optimize your channel for minimal bit errors. Moreover, with the help of the single pulse response analysis method, the effect of equalization can be studied and configured. In this session, you will learn to establish a robust measurement and simulation workflow and get the most signal integrity insight out of your everyday measurement and simulation process. 

Mike Resso, Signal Integrity Application Scientist
Mike Resso is the Signal Integrity Application Scientist in the Component Test Division of Keysight Technologies and has over twenty-five years of experience in the test and measurement industry. His background includes the design and development of electro-optic test instrumentation for aerospace and commercial applications. His most recent activity has focused on the complete multiport characterization of high speed digital interconnects using Time Domain Reflectometry and Vector Network Analysis. He has authored over 30 professional publications including a book on signal integrity. Mike has been awarded one US patent and he received a Bachelor of Science degree in Electrical and Computer Engineering from University of California.

Chun-ting "Tim" Wang Lee, Application Engineer for High Speed Digital applications in the EEsof EDA Group
Chun-ting "Tim" Wang Lee is an Application Engineer for High Speed Digital applications in the EEsof EDA Group of Keysight Technologies. Wang Lee received his BSEE degrees from University of Illinois at Urbana Champaign and MSEE from University of Colorado at Boulder. He is currently a Ph.D candidate focusing on signal integrity research in the Electric Engineering Department at the University of Colorado. In the past years, he has given talks in DesignCon and involved himself with signal integrity projects focusing on improving simulation and measurement correlation.

Thursday February 1
11:05 – 11:45am
Getting the Most Out of DDR4 and Preparing for DDR5 DDR4 was the first DRAM technology to break the High-Speed Digital paradigm that focuses on signal timing and Voh/Vol/Vih/Vil based noise margin analysis. DDR4 speeds demanded an approach more like what’s used in specifying, designing and testing high speed serial interfaces like SATA, USB 3.0 and PCI-Express (up to Gen 3). Timing and voltage thresholds are replaced by eye diagrams, bit error rates and statistical analysis of random jitter and noise, closing a gap between the DDR specification and the behavior of real systems that opened once DDR3 exceeded 1600MT/s. Many memory designers are still climbing this learning curve that is essential to getting the best performance from DDR4 designs at minimum design risk and cost. Right on the heels of DDR4, DDR5 moves the bar even higher to reach speeds where the data eye is completely closed, requiring advanced equalization techniques to open the eye and assure reliable data transfer. This session will help engineers better understand the concepts underlying the DDR4 specification and get the maximum benefits of having a specification that models real system behavior. Then we will extend the discussion to DDR5, to prepare architects, design, and test engineers to take full advantage of its advanced capabilities.

Perry Keller, Lead Digital Applications and Standards Program, Memory Applications Program Manager
Perry Keller is the team lead for Keysight Technologies Digital Applications and Standards Program and Manages its Memory Applications Program. He represents Keysight on the JEDEC and Universal Flash Storage Assn. Boards of Directors and is Chairman of the JEDEC JC40.5 and JC64.5 Logic and UFS Validation Committees as well as the UFSA Compliance Committee.

Perry joined Hewlett Packard in 1980 after graduating from Rice University with a Masters Degree in Electrical Engineering. As HP’s T&M Group evolved into Agilent and then Keysight Technologies, he has served in project management, architecture and R&D roles for hardware, software and ASIC development as well as marketing and product planning for high performance instruments and applications. He lives in Breckenridge, Colorado, and enjoys skiing and mountain biking.