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Sprechen Sie mit einem Experten

Overcome Signal & Power Integrity Design Challenges in the Multi-Gigabit Era

UK seminar tour February May 2017

 
Why do you need Signal Integrity and Power Integrity in one seminar?


Because the success of the physical connection between a transmitter and receiver also depends on the quality of the power that is delivered.
Join this Keysight seminar to learn how to advance your physical layer design to maximize the performance of the next generation of multigigabit links such as DDR, USB, PCIe, HDMI, Ethernet, etc
 

What you will learn?

Using the speed of Keysight’s Channel Simulator along with traditional transient time domain simulation engineers can quickly optimize the design space to maximize margins and identify critical manufacturing details.
Verify the quality of the power delivery network with Keysight’s new PIPro and SIPro simulation technology for accurate IR Drop and parasitic inductances. Learn all about designing for flat impedance to minimize supply noise ripple and EMI.
Throughout the seminar examples will show the power of measurement based models for achieving simulation to measurement correlation. Simple optimization goals can quickly dial in the as-fabricated tolerances. Calibration and de-embedding techniques enable mixing and matching models for full link simulations.
Leave the seminar with the tools you need to verify the physical layer and the signal quality for your next generation serial link.
 

Agenda:

9.00 – Welcome & Introduction

9.30How-to design for Signal Integrity?

  • Signal Integrity Challenges
  • How to use Band Limited Differential S-Parameters
  • Transient IBIS Simulations for DDR
  • IBIS AMI Channel Simulations and the Pulse Response
  • When do I need an EM model of the PCB?

11.00 How-to design for Power Integrity?

  • What is Power Integrity
  • Flat Impedance vs Target Impedance
  • IR Drop and EM Models for PCB parasitics
  • Capacitor Measurement Based Model
  • Voltage Regulator Module Large and Small Signal Modeling

12.30 - Lunch break

13.30 - Signal Integrity and Power Integrity DDR4 Case Study

  • What is Signal Integrity and Power Integrity Co-Simulation
  • Simultaneous Switching Noise in Parallel Bus DDR Type Links
  • Challenges with SI and PI Simulations

15.30 - Wrap-up & Conclusion

Where & When

 

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