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High-Speed Digital Design using ADS

Dear Customer,
Why is high-speed digital design important?
Join us for the HSD Learning event in Oberhaching starting on Tuesday May 9th , 2017!

This training class is designed for engineers with an RF/microwave background who are involved in high-speed mixed-signal design and for engineers with high-level expertise who are looking for improving in-depth knowledge on high-speed digital simulation techniques.
Come and learn more about how to close your design on specification and schedule using the latest HSD Design and Verification solutions.

The schedule is modular; you can register for one or more days as required. These classes cover a large selection of material based on the latest version of ADS and will be led by qualified Keysight instructors. Computers will be provided by Keysight, lunch and refreshments are served during the training days.

Please find below registration information and a detailed agenda. Seating is limited and will be assigned on a first-come, first-served basis. You can consider the registration form as a formal quotation from Keysight. The cost of classes is 490€ per day.

Training Center:

Germany : Oberhaching

Detailed Agenda
Day 1 9AM – 5PM

Introduction to ADS environment and simulation techniques

  • Overview of workspaces, libraries, cells and technologies
    • Lab: Be able to create a workspace, use palettes for design capture, setup and run simulations (Transient and S-Parameter), use tuning, and plot data.
  • Creating Symbols and using Dynamic Model Selection
    • Lab: Be able to add a PDK reference library, cells, schematics and symbols to a workspace. Also, be able to use the library list, dynamic model selection, and plot traces from different datasets onto one plot.
  • Using and understanding the ADS multilayer library
    • Lab: How to use the Multi-Layer Library for Pre-Layout.
  • How to Design PCB Tracks and Vias very quickly in ADS
    • Lab: How to DesiPCB gn Tracks and Vias very quickly in ADS. (Consolidate Signal Integrity design work and other models for Pre-layout)
Day 2 9AM – 5PM Time domain analysis in ADS (REQUIRED: Completion of Day 1)

  • Introduction to Convolution Basics
    • Lab: transform frequency response and S-parameters into impulse response and vice-versa; understand convolution and its controls in ADS-make an S-parameter model from simulation and from measurement
  • Transmission line and Cross Talk modeling
    • Lab: familiarize with the transmission-line libraries available in ADS - effectively use microstrip lines and multi-layer components - use of RLGC models for multi-layer components - understand coupling and observe crosstalk effects (near-end and far-end)- ground and power planes in multi-layer models- observe system resonances
  • Running TDR analysis in ADS
    • Lab: understand the use of ADS for TDR/TDT simulations and measurements- detecting and locating a discontinuity - measuring the characteristic impedance of the line after the discontinuity
Day 3 9AM – 5PM

ADS Channel Simulation for effective system analysis (REQUIRED: Completion of Day 1 & 2)

  • Introduction to Channel simulation using generic Tx and Rx models
  • Channel simulation using IBIS-AMI models
    • Lab: be familiar with IBIS AMI modeling – get insight about Channel Simulation bit by bit and statistical mode – perform crosstalk simulation and manipulate equalization techniques
  • Jitter generation and BER Performance Analysis in ADS
    • Lab: add jitter to your AMI transmitters and perform jitter tolerance on the receiver side
  • Jitter decomposition
    • Lab : Perform Jitter decomposition with different realistic USB3 scenarii, and identify root causes (usage of Infiniiview software from instrumentation world)
Day 4 9AM – 5PM


Allegro Design Flow Integration (ADFI)

  • Introduction to ADFI *
    • Lab : perform Simple PCB design export from Allegro and import it into ADS
  • Customization of the ADFI process
    • Lab : Use the Export Options and customize of Ground and Signal Vias


ODB++Design Flow



  • Introduction to SIPro: A fast way to look at Signal Integrity of high- density, high-layer digital board traces.
  • Perform Import of high layer count Digital Printed Circuit Boards using the SIPro.
  • Create Power Aware SI Analysis, Perform Power Aware SI Analysis and S-Parameters and TDT/TDR results
  • Simulated and analyze critical behaviors of signal integrity (SI) and the performance of signal nets and ground nets to create an EM Channel Model.
Get familiar with the characterization of signal and ground nets of a given channel to create an S-parameter model and generate a schematic view that can be used as the basis of further analysis (e.g. transient and channel simulations).