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Accelerate DDR4/LPDDR3 Memory Debug with Bus level Signal Integrity Insight Webcast

1   Hour | Webcast - enregistré | Où et quand

WHY THIS WEBCAST IS IMPORTANT

High-speed DDR4/LPDDR3 memory designs offer new challenges and increased complexity. Learn about time-saving memory debug and validation techniques using a logic analyzer. Understand how to gain bus level signal integrity insight by interpreting eye scans. Increased insight allows you to make your memory debug go faster and smoother.

Understand how to quickly gain insight into the address, command, and data problems in high-speed memory designs. Review case study examples of logic analyzer eye scans, providing breakthrough bus level integrity insight into DDR3/4, LPDDR2/3 and GDDR5 3.2 Gb/s behavior. Learn new techniques to quickly isolate causes of memory error conditions.

WHO SHOULD ATTEND

High speed DDR3/4, LPDDR2/3 memory design, test, and validation engineers.

PRESENTER

Jennie Grosslight, Memory Test Product Manager, Agilent Technologies

Jennie Grosslight is Keysight’s Memory Test Product Manager where she is responsible for Keysight’s logic analysis and compliance test tools for memory applications. She has worked for HP and Agilent for 20 years in a variety of roles for both oscilloscopes and logic analyzers, including R&D engineer, technical marketing engineer, and product marketing engineer. Jennie has been focused on helping customers analyze and validate memory systems for the past 10 years. She has a degree in Electrical Engineering from the University of Colorado at Colorado Springs.

Où et quand

Price Lieu Pour de plus amples renseignements
Free At Your PC Enroll to view the March 4, 2014 recorded broadcast 

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