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Mastering Signal & Power Integrity Design Challenges for DDR and PCIe Applications

Seminar | Where & When

Mastering Signal & Power Integrity Design Challenges for DDR and PCIe Applications

Seminar to learn design techniques for high speed interconnects


With the increase clock speeds the design of high speed digital interconnects becomes more challenging. Where rules of thumbs may have worked in the past, nowadays you will need to carefully plan your traces and vias in order to get a stable design. Otherwise unwanted effects like jitter, cross-talk and many others may close the eye-diagram and lead to failure of you design.

In this series of seminars we will discuss how to address the design challenges for high speed interconnects like DDR4 and PCIe-3. In a number of technical case studies you will learn tips and tricks on how to improve and optimize your design in both the pre- and post-layout phase in order to minimize risk and reduce PCB iterations and production cost.


The seminar is held in cooperation with Hermann Ruckerbauer, Owner of 'EKH - EyeKnowHow', who has over twenty years of experience in high speed measurement and simulation especially on DRAM related interfaces.




09:00 – 10:00 Latest developments in HSD applications – Learn from an industry expert about latest developments in High-Speed Applications like DDR4, USB 3.1 or PCIe-3 and the corresponding design challenges (Hermann Ruckerbauer)
10:00 – 12:00 Leverage design solutions to address Gigabit challenges in HSD applications (Keysight)
12:00 – 13:00 Lunch
13:00 – 14:30

DDR4 Case study: Time Domain vs. Frequency domain verification of a (LP)DDR4 - Memory interface (Hermann Ruckerbauer)

  • Alternative verification Methods for your Design
  • Understanding DRAMs Basics and important spec parameters
  • Identify Near- and Far-End coupling,Time-skew error
14:30 – 14:45 Coffee break
14:45 – 16:15

PCIe Case study: ComExpress: Simulation of non-standard PCIe channel (Hermann Ruckerbauer)

  • Utilize Pre-Emphasis and equalization in the simulation
  • Understanding PCIe Physical Layer spec and critical parameters like Pre-Emphasis, Equalization and Jitter
  • Evaluate Simulated traces with scope toolsets
16:15 – 16:30 Summary & Price drawing

Where & When

Date(s) Location For more information
2018-03-06 München
2018-03-07 Nürnberg
2018-03-08 Karlsruhe