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New 2014 Keysight EEsof EDA Simulation Tools for Signal Integrity, Power Integrity and EMI/EMC

Signal Integrity DesignWhy this seminar material is important?

While our name has now officially changed to Keysight Technologies, our focus on new product features for the popular Keysight EDA High-Speed Digital products such as Advanced Design System (ADS), EMPro, and SystemVue has not. Originally presented on September 16, 2014, the contents of this seminar cover new features that are enabling today’s high-speed digital engineer to solve the toughest SI/PI/EMC challenges at all stages of the pre-layout, post-layout, measurement design flow. You’ll learn about breakthrough advancements in parallel bus simulators for fast extremely low 1e-16 BER contour DDR4 simulations, and see how the ADS DDR4 Test Bench can generate DDR waveforms for post layout verification using Keysight Technologies' real-time oscilloscope certified Test Compliance software. You will also discover how Keysight’s Controlled Impedance Line Designer (CILD) can help you optimize impedances for maximum eye opening during PCB stack-up design.

There is also content to help you gain a better understanding of potential Electromagnetic Compatibility (EMC)/Electromagnetic Interference (EMI) problems with low voltage high-speed products. Meeting electromagnetic interference (EMI) compliance regulations is a critical step in bringing products to market quickly; one that is made all the more complex by the high-speed signals used to drive today’s digital electronic products. Such high-speed signals can generate unwanted EMI. Learn the latest techniques for overcoming the challenges associated with EMI using the Keysight EMPro FDTD and FEM simulators.

Controlled Impedance Line Designer with Channel Simulation and Optimization

Get a closer look at PCB stack-up design and learn what matters for signal integrity with Keysight’s ADS Controlled Impedance Line Designer. Using the software you can seamlessly leverage the same stack-up for frequency domain, time domain, millions of bits channel, and Electromagnetic simulations.

ADS DDR Test Benches with Waveform Bridge to Instrument Certified DDR Test Compliance

With controllers and DRAMs eating up more of the channel margins for DDR4, the risk of PCB design spins are increasing. Learn how to speed up the design/debug process by using the same industry certified Keysight Infiniium DDR4 Test Compliance Application for both simulated and measured waveforms.

DDR Bus Simulator Breakthrough – DDR4 Simulations

See how EDA simulation can complement and extend the capabilities of instrument DDR4 compliance testing by enabling extremely low 1e-16 BER contour simulations parallel bus DDR architectures with source synchronous clocking.

EMC/EMI Electromagnetic Simulations

Feeling lucky with your next design? Or would you prefer to anticipate any potential problems before your design reaches the final EMC/EMI compliance check, prior to shipping? If so, learn how simulation can help you identify EMC and EMI issues, while avoiding any expensive add-on fixes.

Download the Materials from our Recent Seminar

Seminar Presentations and Papers
Controlled Impedance Line Designer with Channel Simulation and Optimization (PDF, 2.15 MB)
ADS DDR4 Test Benches with Waverform Bridge to Instrument Certified DDR Test Compliance (PDF, 1.41 MB)
DDR Bus Simulator Breakthrough – DDR4 Simulations (PDF, 817 KB)
EMI/EMC Analysis for High Speed Digital Designs (PDF, 3.77 MB)

Additional Example Workspaces from the Presentation Demos

Note: Access to workspace materials for this seminar requires an active license and Knowledge Center login.

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