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HDL Co-Simulation

Hardware Description Language (HDL) Co-Simulation offers an easy-to-use link to HDL simulators, and supports both Verilog and VHDL languages.

The HDL models are user-defined. HDL Co-Simulation enables you to access both the Advanced Design System (ADS) and the HDL simulator graphical user interfaces for data analysis and visualization.

Product Highlights

  • Powerful and accurate system verification with built-in, mixed-signal processing capability from baseband to RF
  • Simplified User Interface makes the usage of multiple simulators easy
  • Tight interaction between Advanced Design System (ADS) and the HDL design for rapid design, debug, and co-verification
  • Integrated design flow from system design to ASIC/FPGA implementation

HDL Co-Simulation helps ensure the successful development of system-on-chip (SOC) or application-specific integrated circuits (ASICs) at the sytem level, using Verilog HDL or VHDL in conjunction with circuit behavioral models. With HDL Co-simulation, you can easily incorporate existing or off-the-shelf HDL code and associated intellectual property (IP) into your designs. This feature enables you to efficiently leverage past work and verify complete designs before committing them to silicon.

HDL Co-Simulation is integrated into the Ptolemy Element.