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Boundary Scan / JTAG

In the context of electronics manufacturing test, Boundary Scan technology is more commonly associated with the technology that allows the testing of the interconnection between integrated circuits. The testing is primarily focused on finding defects of short-circuits and/or open-circuits and relies on the boundary scan cells that are designed into each pin of the integrated circuit. These boundary scan cells can be either input cells, output cells or bidirectional cells. With this ability to drive and/or receive signals on the pin level and using the Agilent's unique pattern-generation algorithm, users are able to pin-point the location of the defect.

The Joint Test Action Group (JTAG), made up of mutual interest companies standardized this technology into the IEEE 1149.1 standard which was released in 1990. That is why Boundary Scan is sometimes also referred to as JTAG.

Agilent continued to innovate over the years to come up with derivative solutions that are based on the IEEE 1149.1 standard such as Cover-Extend Technology (CET) which uses capacitive sensing plates to pick up stimulus signals from driving Boundary Scan devices, Silicon Nails which allows the testing of non-Boundary Scan devices, Dot6 which tests high-speed differential signals and many more.