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RF SiP/Module Design Flows

The RF System-in-Package (SiP) designer obtains specifications from the system designer, then evaluates, mix-and-matches (to use best-in-class technology), and optimizes each functional block to meet the system requirements for an optimum performance versus cost. Algorithm and system level verification tools such as, Keysight Ptolemy, SystemVue and Spectrasys may be extensively used in this step.

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RF SiP/Module Design Flow

The individual chip of multiple ICs may be designed in the RFIC/MMIC design flows with different Process Design Kits (PDKs) or modeled as a behavioral model for a faster and higher level simulation.

The designer enters a schematic in Advanced Design System (ADS) for packaging, interconnects, surface-mount technology (SMT), and embedded passives, and may simulate performance using a variety of frequency domain (linear, non-linear, Circuit Envelope) and time domain (SPICE, synchronous data-flow, timed-synchronous dataflow) simulation technologies. Several of these technologies are patented or proprietary to Keysight. In this step, the RF SiP/Module designer may utilize highly accurate industry standard ADS models, qualified component vendor libraries, and physical component models generated by Advanced Model Composer (AMC) with electromagnetic (EM) simulators to improve the quality of simulations. Once the initial simulation results are satisfactory, the designer can design physical layouts for individual passive components to transform electrical designs to physical designs. These components are then simulated with EM simulators and verified to the desired component characteristics and values. The components may be stored and re-used for future designs. Also, the full or partial layout may need to be simulated with the EM simulators in order to predict and debug any unwanted coupling, parasitic effects, and/or ground sharing problems. The layout may need to be modified as a result of these simulations.

Also many of design tools, like filter synthesis, facilitate the design process. The critical part of the design, such as embedded passive components and various interconnects, may be simulated with 3D EM simulators in ADS to ensure the highest accuracy of simulation results. These designs or simulations can then be co-simulated with Ptolemy.

The layout may need to be modified as a result of these simulations. When the layout is completed, a layout-versus-schematic (LVS) representation check or design rule check (DRC) can be performed. Layout checking in ADS includes nodal and connectivity checks through the ADS connectivity engine, and DRC completed through ADS DRC engine.

Once the layout is checked it is exported along with applicable drill patterns for manufacturing purposes. Once the part is assembled, performance may be verified using ADS Connected Solutions which performs testing on the part using the same "measurements" used in circuit simulation. This is an effective methodology for custom or proprietary testing where no canned solution exists.

Keysight EEsof EDA supports two design flows, ADS Driven RF SiP/Module Design Flow and ADS Linked RF SiP/Module Design Flow, as shown below.

ADS Driven RF SiP/Module Design Flow

ADS Driven Design Flow

ADS Linked RF SiP/Module Design Flow

ADS Linked Design Flow

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