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Solving Power Integrity & Signal Integrity Design Challenges Seminar

Design margins are decreasing rapidly with low power IOT devices, multi-level PAM4 400 Gigabit Ethernet, and high reliability automotive systems. Your ability to leverage a data sheet design may no longer work. Today, simulation and measurement techniques must work together to solve the Power Integrity (PI) and Signal Integrity (SI) challenges of your next design.

Characterization and Optimization of Via Designs using Z-input Impedance

This paper discusses a simple, but very effective Z input impedance method that augments the traditional TDR method for characterizing and optimizing via designs in much faster speed systems. 

> Slides (PDF, 3.91 MB)

ADS Interconnect Toolbox - Via Designer

This paper discusses the flow and application examples of ADS Interconnect Toobox, which includes Controlled Impedance Line Designer (CILD) and Via Designer.

> Slides (PDF, 1.76 MB)

> Workspaces (7zads,  42.3 MB)

PIPro DC Electro-Thermal Insights for PCB Applications

This paper discusses the PCB thermal effect such as increased DC IR-Drop due to temperature rise and how to mitigate it.

> Slides (PDF, 4.39 MB)

> Workspaces (7zads, 124.9 MB)

Simulation to Measurement Challenges on PAM4 for 400GB Ethernet

This paper discusses PAM4 signaling, IBIS-AMI modeling, Interconnect application space for 400G Ethernet with an application example.  

> Slides (PDF, 3.81 MB)

Optimizing PDN DeCaps for Noise and EMI

This paper discusses the theory and methodology to design flat impedance for power delivery networks.

> Slides (PDF, 5.95 MB)

> Workspaces (7zads, 13.8 MB)

> README (PDF, 3.09 MB) 
 

DDR5 Exploration with Simulation

This paper discusses the design challenges for DDR5 and introduces Keysight EDA DDR solutions. 

> Slides (PDF, 4.30 MB)

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