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What is the raw jitter tolerance for the N4960A/N4952A?

There is no CDR in the N4960A, so by itself, the JTOL plot will be a flat line somewhere below 1 UI.

An external CDR can be used:

  • Connect the recovered clock to the delayed clock input port on the front panel of the N4960A.
  • The delayed clock source needs to be set to external, and the expected clock frequency needs to be entered (there is no frequency counter on the delayed clock input port, so you need to tell it what to expect).


This plot from the data sheet (N4960A Serial BERT 17 and 32 Gb/s - Data Sheet) shows the guaranteed JTOL performance.

You’ll note that above 30 MHz modulation frequency the jitter amplitude drops quite a bit. This is the guaranteed minimum JTOL level that the system will run error free at, and in most cases, you will get better performance than this. The generator side can generate up to 100 UI LF jitter and up to 1 UI HF jitter.