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For Xilinx FPGA Dynamic Probe, when should I use Xilinx Core Generator instead of Core Inserter?

The Agilent Trace Core (ATC2) is inserted into a user design using the standard Integrated Logic Analyzer (ILA) insertion flows. The main flow is to add a core using ChipScope Core Generator or ChipScope Core Inserter tool. These tools are standard with a ChipScope installation.

Also available for core insertion is the Synplicity Certify tool. This tool allows the user to insert cores graphically and then calls the Core Generator in the background to create all tools and then generates a signal name file (.CDC). Once the cores are inserted they are synthesized and then run through the “Place and Route” tools.

Core Generator is usually preferable if you need partitions, since Core Inserter does not support partitions. Core Generator does support partitions but is much less convenient.

When the cores are inserted using the Core Generator, the user is required to do much manual interaction. For the Core Generator flow, the user first generates the appropriate ATC2 core, sized properly with pins assigned. Also, the user must generate an Integrated Controller (ICON) core to connect the ATC2 core.

Once inserted, the user adds "black-box" instantiations into their design in the locations where they want observability. Once added, the user then either manually edits a CDC file to fill in the signal names connected to ATC2, or they can use the default signal names assigned by the logic analyzer.

As mentioned, an alternate way to add cores is through Core Inserter. Core Inserter takes a synthesized design and inserts cores at user-specified locations. Core Inserter does this by reading in the synthesized netlist file, known as the EDIF file, and then displaying all nets to the user. The user then chooses what type of debug cores they want to use and they configure these cores by connecting their inputs with the signals that they want to probe (make observable). The difference between this and the previous insertion method is that a CDC file is created as the user selects signals. Here the signals connected to the inputs of the core, for instance an ATC2 core, are written to the CDC file when the user presses the Insert Core button in the UI. Thus the inserter flow takes care of logic analyzer setup through the CDC file.

Once the ATC2 core is inserted, different or more nodes can be analyzed with two methods. The first method of re-probing is to reconnect the ATC2 inputs to different signals by either changing the HDL connection for the Core Generator flow, or re-running Core Inserter and changing signal probes in the tool. However, re-probing by this method does require the user to run “Place and Route” and potentially synthesis (for Core Generator flow), a limitation that may be very time consuming.

An alternative is to re-probe nets using FPGA Editor. With this type of re-probing you actually edit the placed design and modify the connections to the ATC2 core. If only a few signals need re-probing, this can be a very efficient way of observing a new set of internal signals.