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PathWave Design Seminar: Design a Smaller, Lighter, and Lower Cost Switched Mode Power Supply

The increasing demand for reliable, low cost, high power density power electronics is driving up the edge speed (di/dt) of switched mode power supplies. In this high di/dt era, layout parasitics become increasingly troublesome. Traditional design techniques are not adequate. A new methodology that adds post-layout design and simulation is required. In this seminar, we will present four papers that address these challenges:

  • Introduction to Designing Switched-Mode Power Supplies in the High di/dt Era
  • Controlling Post-layout Parasitic Effects
  • Understanding and Controlling EMI
  • Optimizing Closed Loop Performance

This seminar will illustrate how to overcome these issues using ADS circuit simulators and field solvers.

Intro: Designing Switched-Mode Power Supplies in the High di/dt Era

Engineers building switched-mode power supplies into their systems demand lower cost, smaller size, and lighter weight. Three components dominate the design challenge: the heat sink, the inductor, and the capacitor. Traditional workflows don't work in the high di/dt era because they are blind to the spike voltages induced across layout parasitics. This paper discusses a post-layout analysis step to the workflow between the pre-layout circuit simulation and physical prototyping steps.

> Slides (PDF, 2.38 MB)

> Technical Seminar Video 

Controlling Parasitic Effects

Post-layout parasitic effects that degrade performance and can cause failure — skin depth, proximity effect, spike/surge voltage (sometimes called conducted EMI), noise, ringing, oscillations, and false triggering. All physical implementations include these parasitics to some extent, and their impact is not visible with pre-layout schematic circuit simulation. You will learn how to use ADS and high-speed design techniques to verify, troubleshoot, and optimize your post-layout design.

> Slides (PDF, 3.11 MB)

> Technical Seminar Video 

Understanding and Controlling EMI

High-speed switched-mode power supplies produce noise (conducted and radiated EMI) that can interfere with other electronics and degrade system performance and reliability. Also, this circuit must function correctly even in the presence of inbound interference from its environment, again both conducted and radiated. In this paper, we advocate a different approach; post-layout simulation of EMC as part of the design process.

> Slides (PDF, 6.60 MB)

> Technical Seminar Video 

Optimizing Closed Loop Performance

There are many textbooks, papers, and materials on closed-loop control design for switched-mode power supplies (SMPSs). In this paper, you will learn about mechanisms which cause designs to diverge from a typical textbook closed-loop performance, new techniques which can provide insights into problems, and how to correct issues before fabrication through an improved workflow.

> Slides (PDF, 4.59 MB)

> Technical Seminar Video 

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